Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5986
-gerrit
commit 8375b843cba36297882c250b9c7e0b6b8594a284 Author: Martin Roth martin.roth@se-eng.com Date: Thu Jun 12 12:38:34 2014 -0600
fsp_baytrail: Add Baytrail B0/B1 "Super SKU" microcode
- Add the Bay Trail B0/B1 microcode. These versions of the SOC were released as a "Super SKU" which had features of all the different SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the number 2 in the third character from the left in the microcode name.
- Update the size of the microcode blob. We should be pushing a patch to eliminate the need for this shortly.
Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191 Signed-off-by: Martin Roth martin.roth@se-eng.com --- src/soc/intel/fsp_baytrail/Kconfig | 2 +- src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 870147e..bce5542 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -102,7 +102,7 @@ config CPU_MICROCODE_CBFS_LOC
config CPU_MICROCODE_CBFS_LEN hex - default 0xcc00 + default 0x19800 help This should be updated when the microcode patch changes.
diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 9df84dd..43cbf00 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,7 +19,8 @@
unsigned microcode[] = {
-/* Size is 0xCC00 - update in Kconfig when the patch gets updated. */ +/* Size is 0x19800 - update in Kconfig when the patch gets updated. */ +#include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 #include "M013067331E.h" // M0130673: Baytrail I B2 / B3
};