Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74532 )
(
5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override ......................................................................
soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override
This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between UFS and non-UFS to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending HECI command.
TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting to google/marasov.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74532 Reviewed-by: Tarun Tuli taruntuli@google.com Reviewed-by: Kapil Porwal kapilporwal@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/alderlake/chip.c 1 file changed, 42 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved Kapil Porwal: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 7cdeb7c..f052279 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -162,6 +162,26 @@ } #endif
+#if CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) +/* + * SoC override API to identify if ISH Firmware existed inside CSE FPT. + * + * SoC with UFS enabled would like to keep ISH enabled as well, hence + * identifying the UFS enabled device is enough to conclude that the ISH + * partition also is available. + */ +bool soc_is_ish_partition_enabled(void) +{ + struct device *ufs = pcidev_path_on_root(PCH_DEVFN_UFS); + uint16_t ufs_pci_id = ufs ? pci_read_config16(ufs, PCI_DEVICE_ID) : 0xFFFF; + + if (ufs_pci_id == 0xFFFF) + return false; + + return true; +} +#endif + /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ static void soc_fill_gpio_pm_configuration(void) {