Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25603
Change subject: nb/intel/i945: Put stage cache in TSEG ......................................................................
nb/intel/i945: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages.
Untested.
Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/Makefile.inc A src/northbridge/intel/i945/stage_cache.c 3 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/25603/1
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 05e2d49..9b3777b 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -30,6 +30,7 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select SMM_TSEG select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n @@ -89,4 +90,14 @@ On other boards the check always creates a false positive, effectively making it impossible to resume.
+config SMM_RESERVED_SIZE + hex + default 0x100000 + +# Intel Enhanced Debug region must be 4MB +config IED_REGION_SIZE + hex + default 0x400000 + + endif diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 0e4fcfc..0772212 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -29,4 +29,7 @@
smm-y += udelay.c
+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + endif diff --git a/src/northbridge/intel/i945/stage_cache.c b/src/northbridge/intel/i945/stage_cache.c new file mode 100644 index 0000000..e1e2ffb --- /dev/null +++ b/src/northbridge/intel/i945/stage_cache.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <stage_cache.h> +#include "i945.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; +#ifdef __SIMPLE_DEVICE__ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0x00, 0), ESMRAMC); +#else + const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), + ESMRAMC); +#endif + const u32 tseg_size = decode_tseg_size(esmramc); + *base = (void *)((uintptr_t)cbmem_top() + tseg_size + - CONFIG_SMM_RESERVED_SIZE - CONFIG_IED_REGION_SIZE); +}