[coreboot-gerrit] [M] Change in coreboot[main]: soc/amd/common/psp/psp_smi_flash: implement generation 1 support

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84064?usp=email )

Change subject: soc/amd/common/psp/psp_smi_flash: implement generation 1 support
......................................................................

soc/amd/common/psp/psp_smi_flash: implement generation 1 support

Implement the request buffer access functions for the PSP generation 1
case. In this case, only the SMI_TARGET_NVRAM is supported, so always
return this target NV ID and always return true in the validity check
which in the generation 2 case checks if the target NV ID is valid.

Signed-off-by: Felix Held 
Change-Id: I7e141f846e930bab6972a281745c0180ac52c291
---
M src/soc/amd/common/block/psp/Makefile.mk
A src/soc/amd/common/block/psp/psp_smi_flash_gen1.c
2 files changed, 54 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/84064/1

diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk
index 20e55e8..937cb8e 100644
--- a/src/soc/amd/common/block/psp/Makefile.mk
+++ b/src/soc/amd/common/block/psp/Makefile.mk
@@ -17,7 +17,9 @@

romstage-y += psp_gen1.c
 ramstage-y += psp_gen1.c
+
 smm-y += psp_gen1.c
+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi_flash_gen1.c

endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1

diff --git a/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c b/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c
new file mode 100644
index 0000000..c9beddb
--- /dev/null
+++ b/src/soc/amd/common/block/psp/psp_smi_flash_gen1.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <types.h>
+#include "psp_def.h"
+#include "psp_smi_flash.h"
+
+bool is_valid_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf)
+{
+	return true;
+}
+
+bool is_valid_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf)
+{
+	return true;
+}
+
+bool is_valid_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf)
+{
+	return true;
+}
+
+u64 get_psp_spi_info_id(struct mbox_psp_cmd_spi_info *cmd_buf)
+{
+	return SMI_TARGET_NVRAM;
+}
+
+void set_psp_spi_info(struct mbox_psp_cmd_spi_info *cmd_buf, u64 lba, u64 block_size,
+		      u64 num_blocks)
+{
+	write64(&cmd_buf->req.lba, lba);
+	write64(&cmd_buf->req.block_size, block_size);
+	write64(&cmd_buf->req.num_blocks, num_blocks);
+}
+
+void get_psp_spi_read_write(struct mbox_psp_cmd_spi_read_write *cmd_buf, u64 *target_nv_id,
+			    u64 *lba, u64 *offset, u64 *num_bytes, u8 **data)
+{
+	*target_nv_id = SMI_TARGET_NVRAM;
+	*lba = read64(&cmd_buf->req.lba);
+	*offset = read64(&cmd_buf->req.offset);
+	*num_bytes = read64(&cmd_buf->req.num_bytes);
+	*data = cmd_buf->req.buffer;
+}
+
+void get_psp_spi_erase(struct mbox_psp_cmd_spi_erase *cmd_buf, u64 *target_nv_id, u64 *lba,
+		       u64 *num_blocks)
+{
+	*target_nv_id = SMI_TARGET_NVRAM;
+	*lba = read64(&cmd_buf->req.lba);
+	*num_blocks = read64(&cmd_buf->req.num_blocks);
+}