[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add restore and enable GPIO PM

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41712 )

Change subject: soc/intel/common: Add restore and enable GPIO PM
......................................................................

soc/intel/common: Add restore and enable GPIO PM

Enable GPIO clock gating when enter s0ix/Sx and save the PM bits.
Restore the PM bits when exit s0ix/Sx. This reference CB:37685.

BUG=b:157280323
TEST=Check GPIO PM bits when enter/exit s0ix are expected

Signed-off-by: Eric Lai 
Change-Id: If5e4553d568a872de234a2d671118acbae0a6159
---
M src/soc/intel/common/acpi/gpio.asl
1 file changed, 42 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/41712/1

diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl
index dbfa7af..7176334 100644
--- a/src/soc/intel/common/acpi/gpio.asl
+++ b/src/soc/intel/common/acpi/gpio.asl
@@ -16,3 +16,45 @@
    	PCRO (Local0, GPIO_MISCCFG,  Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG)
    }
 }
+
+
+/* GPIO Power Management bits */
+Name(GPMB, Package(TOTAL_GPIO_COMM) {0})
+
+/*
+ * Save GPIO Power Management bits
+ */
+Method (SGPM, 0, Serialized)
+{
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		Local1 = GPID (Local0)
+		GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG)
+	}
+}
+
+/*
+ * Restore GPIO Power Management bits
+ */
+Method (RGPM, 0, Serialized)
+{
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		CGPM (Local0, DerefOf(GPMB[Local0]))
+	}
+}
+
+/*
+ * Save current setting of GPIO Power Management bits and
+ * enable all Power Management bits for all communities
+ */
+Method (EGPM, 0, Serialized)
+{
+	/* Save current setting and will restore it when resuming */
+	SGPM ()
+	/* Enable PM bits */
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	}
+}