Attention is currently required from: Maciej Pijanowski, Michał Żygowski, Paul Menzel.
Hello Michał Żygowski, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80608?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/fast_spi: probe for 2nd flash component ......................................................................
soc/intel/common/block/fast_spi: probe for 2nd flash component
Fast SPI code assumes only one SPI flash is present. The SPI flash driver for older southbridges is able to detect multichip. See the spi_is_multichip() in src/southbridge/intel/common/spi.c.
Some boards (e.g. Lenovo ThinkCentre M920 Tiny) still come with two chips populated instead of one. With this change, both chips are probed, and the correct total size is calculated. Otherwise, only the first one was probed, which resulted in an error such as:
SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!!
Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Signed-off-by: Maciej Pijanowski maciej.pijanowski@3mdeb.com --- M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/fast_spi/fast_spi_flash.c 2 files changed, 31 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/80608/3