Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52844 )
Change subject: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration ......................................................................
soc/intel/tigerlake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause.
Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/52844 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 5 insertions(+), 11 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index c788fc4..a3ce68a 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -393,17 +393,11 @@ params->DisableTccoldOnUsbConnected = 1;
/* Chipset Lockdown */ - if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - params->PchLockDownGlobalSmi = 0; - params->PchLockDownBiosInterface = 0; - params->PchUnlockGpioPads = 1; - params->RtcMemoryLock = 0; - } else { - params->PchLockDownGlobalSmi = 1; - params->PchLockDownBiosInterface = 1; - params->PchUnlockGpioPads = 0; - params->RtcMemoryLock = 1; - } + const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; + params->PchLockDownGlobalSmi = lockdown_by_fsp; + params->PchLockDownBiosInterface = lockdown_by_fsp; + params->PchUnlockGpioPads = !lockdown_by_fsp; + params->RtcMemoryLock = lockdown_by_fsp;
/* coreboot will send EOP before loading payload */ params->EndOfPostMessage = EOP_DISABLE;