Julius Werner (jwerner@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13668
-gerrit
commit 6c398ea7f4194fe829f8b892f3065c8114289d97 Author: Julius Werner jwerner@chromium.org Date: Tue Feb 9 23:10:17 2016 -0800
tegra132/pistachio: Increase romstage size in memlayout.ld
These SoCs have come within a kilobyte of their romstage limit, so let's expand that a little to make room for future core code contributions. (In the Tegra case just by copying the layout from 132, because why not? Keeps things simple.)
BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos for Foster, Rush, Ryu, Smaug and Urara.
Change-Id: If8c1ea81cf9827412c78d67a09d54e7a2dc044ac Signed-off-by: Julius Werner jwerner@chromium.org --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 6 +++--- src/soc/nvidia/tegra132/include/soc/memlayout.ld | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index c84de40..a9800a5 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -36,9 +36,9 @@ SECTIONS * and then through the identity mapping in ROM stage. */ SRAM_START(0x1a000000) - ROMSTAGE(0x1a005000, 40K) - VBOOT2_WORK(0x1a00f000, 12K) - PRERAM_CBFS_CACHE(0x1a012000, 56K) + ROMSTAGE(0x1a005000, 60K) + VBOOT2_WORK(0x1a014000, 12K) + PRERAM_CBFS_CACHE(0x1a017000, 56K) SRAM_END(0x1a066000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping. diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld index e3d221e..a8f8a34 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld @@ -29,17 +29,17 @@ SECTIONS { SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) - PRERAM_CBFS_CACHE(0x40002000, 72K) - VBOOT2_WORK(0x40014000, 12K) + PRERAM_CBFS_CACHE(0x40002000, 36K) + VBOOT2_WORK(0x4000B000, 12K) #if ENV_ARM64 - STACK(0x40017000, 3K) + STACK(0x4000E000, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ - STACK(0x40017C00, 3K) + STACK(0x4000EC00, 3K) #endif - TIMESTAMP(0x40018800, 2K) - BOOTBLOCK(0x40019000, 22K) - VERSTAGE(0x4001e800, 55K) - ROMSTAGE(0x4002c400, 77K) + TIMESTAMP(0x4000F800, 2K) + BOOTBLOCK(0x40010000, 28K) + VERSTAGE(0x40017000, 64K) + ROMSTAGE(0x40027000, 100K) SRAM_END(0x40040000)
DRAM_START(0x80000000)