HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46281 )
Change subject: nb/intel/ironlake: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ......................................................................
nb/intel/ironlake: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
Change-Id: If8f30f558c422d1168efd218759a406b26338ef5 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/ironlake/finalize.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 3 files changed, 103 insertions(+), 116 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46281/1
diff --git a/src/northbridge/intel/ironlake/finalize.c b/src/northbridge/intel/ironlake/finalize.c index 88bc98d..6b91965 100644 --- a/src/northbridge/intel/ironlake/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -4,13 +4,13 @@
void intel_ironlake_finalize_smm(void) { - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1 << 31); - MCHBAR32_OR(0x7000, 1 << 31); - MCHBAR32_OR(0x77fc, 1 << 0); + mchbar32_or(0x5500, 1 << 0); /* PAVP */ + mchbar32_or(0x5f00, 1 << 31); /* SA PM */ + mchbar32_or(0x6020, 1 << 0); /* UMA GFX */ + mchbar32_or(0x63fc, 1 << 0); /* VTDTRK */ + mchbar32_or(0x6800, 1 << 31); + mchbar32_or(0x7000, 1 << 31); + mchbar32_or(0x77fc, 1 << 0);
/* Memory Controller Lockdown */ MCHBAR8(0x50fc) = 0x8f; diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index b9e5322..4d30500 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -98,19 +98,6 @@ #define MSAC 0x62 /* Multi Size Aperture Control */
/* - * MCHBAR - */ - -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -/* * EPBAR - Egress Port Root Complex Register Block */
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 05323f1..fe20c8c 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -323,10 +323,10 @@ MCHBAR8(0x5ff) = 0x0; MCHBAR8(0x5ff) = 0x80; MCHBAR32(0x580 + (channel << 10)) = 0x8493c012 | addr; - MCHBAR8_OR(0x580 + (channel << 10), 1); + mchbar8_or(0x580 + (channel << 10), 1); while (!((ret = MCHBAR32(0x580 + (channel << 10))) & 0x10000)) ; - MCHBAR8_AND(0x580 + (channel << 10), ~1); + mchbar8_unset(0x580 + (channel << 10), 1); return ret; }
@@ -478,7 +478,7 @@ } }
- MCHBAR32_OR(0x130, 1); + mchbar32_or(0x130, 1); while (MCHBAR8(0x130) & 1) ; } @@ -1235,7 +1235,7 @@ if (MCHBAR8(0x2ca9) & 1) some_delay_3_half_cycles = 3; for (channel = 0; channel < NUM_CHANNELS; channel++) { - MCHBAR32_OR(0x220 + (channel << 10), 0x18001117); + mchbar32_or(0x220 + (channel << 10), 0x18001117); MCHBAR32(0x224 + (channel << 10)) = (info->max_slots_used_in_channel - 1) | ((info->cas_latency - 5 - info->clock_speed_index) @@ -1258,7 +1258,7 @@
MCHBAR8(0x267 + (channel << 10)) = 0x4; MCHBAR16(0x272 + (channel << 10)) = 0x155; - MCHBAR32_AND_OR(0x2bc + (channel << 10), 0xFF000000, 0x707070); + mchbar32_unset_and_set(0x2bc + (channel << 10), 0x00ffffff, 0x707070);
write_500(info, channel, ((!info->populated_ranks[channel][1][1]) @@ -1332,8 +1332,8 @@
MCHBAR16(0x610) = (MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) | (MCHBAR16(0x610) & 0x1C3) | 0x3C; - MCHBAR16_OR(0x612, 0x100); - MCHBAR16_OR(0x214, 0x3E00); + mchbar16_or(0x612, 0x100); + mchbar16_or(0x214, 0x3E00); for (i = 0; i < 8; i++) { pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), (info->total_memory_mb - 64) | !i | 2); @@ -2227,7 +2227,7 @@ write_1d0(reg1b3 ^ 32, 0x1b3, 6, 1); write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1); failmask = check_testing(info, total_rank, 0); - MCHBAR32_OR(0xfb0, 0x00030000); + mchbar32_or(0xfb0, 0x00030000); do_fsm(state, count, failmask, 5, 47, lower_usable, upper_usable, reg1b3); } @@ -2292,7 +2292,7 @@ check_testing_type2(info, total_rank, 3, i, 1); } - MCHBAR32_OR(0xfb0, 0x00030000); + mchbar32_or(0xfb0, 0x00030000); for (lane = 0; lane < 8; lane++) if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { @@ -2393,7 +2393,7 @@ 1); }
- MCHBAR32_OR(0xfb0, 0x00030000); + mchbar32_or(0xfb0, 0x00030000); for (lane = 0; lane < 8; lane++) { if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { @@ -3520,8 +3520,8 @@ 2 * info->cas_latency - 7 + 11); delay_d_ps += info->revision >= 8 ? 2758 : 4428;
- MCHBAR32_AND_OR(0x140, 0xfaffffff, 0x2000000); - MCHBAR32_AND_OR(0x138, 0xfaffffff, 0x2000000); + mchbar32_unset_and_set(0x140, 0x05000000, 0x2000000); + mchbar32_unset_and_set(0x138, 0x05000000, 0x2000000); if ((MCHBAR8(0x144) & 0x1f) > 0x13) delay_d_ps += 650; delay_c_ps = delay_d_ps + 1800; @@ -3580,9 +3580,9 @@ info->training.reg274265[channel][2] << 8; } if (info->training.reg2ca9_bit0) - MCHBAR8_OR(0x2ca9, 1); + mchbar8_or(0x2ca9, 1); else - MCHBAR8_AND(0x2ca9, ~1); + mchbar8_unset(0x2ca9, 1); }
static void restore_274265(struct raminfo *info) @@ -3597,9 +3597,9 @@ info->cached_training->reg274265[channel][2] << 8; } if (info->cached_training->reg2ca9_bit0) - MCHBAR8_OR(0x2ca9, 1); + mchbar8_or(0x2ca9, 1); else - MCHBAR8_AND(0x2ca9, ~1); + mchbar8_unset(0x2ca9, 1); }
static void dmi_setup(void) @@ -3607,7 +3607,7 @@ gav(DMIBAR8(0x254)); DMIBAR8(0x254) = 0x1; DMIBAR16(0x1b8) = 0x18f2; - MCHBAR16_AND_OR(0x48, 0, 0x2); + mchbar16_unset_and_set(0x48, 0xffff, 0x2);
DMIBAR32(0xd68) |= 0x08000000;
@@ -3634,7 +3634,7 @@ MCHBAR16(0x1170) = 0xa880; MCHBAR8(0x11c1) = 0x1; MCHBAR16(0x1170) = 0xb880; - MCHBAR8_AND_OR(0x1210, 0, 0x84); + mchbar8_unset_and_set(0x1210, 0xff, 0x84);
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { /* 0 for 32MB */ @@ -3651,9 +3651,9 @@ if (deven & 8) { MCHBAR8(0x2c30) = 0x20; pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18 - MCHBAR16_OR(0x2c30, 0x200); + mchbar16_or(0x2c30, 0x200); MCHBAR16(0x2c32) = 0x434; - MCHBAR32_AND_OR(0x2c44, 0, 0x1053687); + mchbar32_unset_and_set(0x2c44, 0xffffffff, 0x1053687); pci_read_config8(GMA, MSAC); // = 0x2 pci_write_config8(GMA, MSAC, 0x2); read8(DEFAULT_RCBA + 0x2318); @@ -3662,7 +3662,7 @@ write8(DEFAULT_RCBA + 0x2320, 0xfc); }
- MCHBAR32_AND_OR(0x30, 0, 0x40); + mchbar32_unset_and_set(0x30, 0xffffffff, 0x40);
pci_write_config16(NORTHBRIDGE, GGC, ggc); gav(read32(DEFAULT_RCBA + 0x3428)); @@ -3815,7 +3815,7 @@ /* after SPD */ timestamp_add_now(102);
- MCHBAR8_AND(0x2ca8, 0xfc); + mchbar8_unset(0x2ca8, 3);
collect_system_info(&info); calculate_timings(&info); @@ -3851,9 +3851,9 @@ MCHBAR16(0x2c20) = 0x10; }
- MCHBAR32_OR(0x18b4, 0x210000); - MCHBAR32_OR(0x1890, 0x2000000); - MCHBAR32_OR(0x18b4, 0x8000); + mchbar32_or(0x18b4, 0x210000); + mchbar32_or(0x1890, 0x2000000); + mchbar32_or(0x18b4, 0x8000);
gav(pci_read_config32(QPI_PHY_0, QPI_PLL_STATUS)); // !!!! pci_write_config8(QPI_PHY_0, QPI_PLL_RATIO, 0x12); @@ -3861,10 +3861,10 @@ gav(MCHBAR16(0x2c10)); MCHBAR16(0x2c10) = 0x412; gav(MCHBAR16(0x2c10)); - MCHBAR16_OR(0x2c12, 0x100); + mchbar16_or(0x2c12, 0x100);
gav(MCHBAR8(0x2ca8)); // !!!! - MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080); + mchbar32_unset_and_set(0x1804, 0x00000003, 0x8400080);
pci_read_config32(QPI_PHY_0, QPI_PHY_CONTROL); // !!!! pci_write_config32(QPI_PHY_0, QPI_PHY_CONTROL, 0x40a0a0); @@ -3872,7 +3872,7 @@ gav(MCHBAR32(0x1804)); // !!!!
if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); + mchbar8_or(0x2ca8, 1); }
MCHBAR32(0x18d8) = 0x120000; @@ -3894,13 +3894,13 @@ gav(MCHBAR32(0x18dc)); // !!!!
if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); // guess + mchbar8_or(0x2ca8, 1); // guess }
MCHBAR32(0x188c) = 0x20bc09; pci_write_config32(QPI_PHY_0, QPI_PHY_PWR_MGMT, 0x40b0c09); MCHBAR32(0x1a10) = 0x4200010e; - MCHBAR32_OR(0x18b8, 0x200); + mchbar32_or(0x18b8, 0x200); gav(MCHBAR32(0x1918)); // !!!! MCHBAR32(0x1918) = 0x332;
@@ -3910,17 +3910,17 @@ MCHBAR32(0x182c) = 0x10202; gav(pci_read_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT)); // !!!! pci_write_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT, 0x10202); - MCHBAR32_AND(0x1a1c, 0x8fffffff); - MCHBAR32_OR(0x1a70, 0x100000); + mchbar32_unset(0x1a1c, 0x70000000); + mchbar32_or(0x1a70, 0x100000);
- MCHBAR32_AND(0x18b4, 0xffff7fff); + mchbar32_unset(0x18b4, 0x00008000); gav(MCHBAR32(0x1a68)); // !!!! MCHBAR32(0x1a68) = 0x343800; gav(MCHBAR32(0x1e68)); // !!!! gav(MCHBAR32(0x1a68)); // !!!!
if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); // guess + mchbar8_or(0x2ca8, 1); // guess }
pci_read_config32(QPI_LINK_0, QPI_QPILCL); // !!!! @@ -3936,7 +3936,7 @@ gav(MCHBAR32(0x1af0)); // !!!!
if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); // guess + mchbar8_or(0x2ca8, 1); // guess }
gav(MCHBAR32(0x1890)); // !!!! @@ -3974,14 +3974,14 @@ set_2dxx_series(&info, s3resume);
if (!(deven & 8)) { - MCHBAR32_AND_OR(0x2cb0, 0, 0x40); + mchbar32_unset_and_set(0x2cb0, 0xffffffff, 0x40); }
udelay(1000);
if (deven & 8) { - MCHBAR32_OR(0xff8, 0x1800); - MCHBAR32_AND(0x2cb0, 0x00); + mchbar32_or(0xff8, 0x1800); + mchbar32_unset(0x2cb0, 0xffffffff); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e); @@ -4040,11 +4040,11 @@ MCHBAR16(0x11c0) = 0xc40b; MCHBAR16(0x11c2) = 0x303; MCHBAR16(0x11c4) = 0x301; - MCHBAR32_AND_OR(0x1190, 0, 0x8900080a); + mchbar32_unset_and_set(0x1190, 0xffffffff, 0x8900080a); MCHBAR32(0x11b8) = 0x70c3000; MCHBAR8(0x11ec) = 0xa; MCHBAR16(0x1100) = 0x800; - MCHBAR32_AND_OR(0x11bc, 0, 0x1e84800); + mchbar32_unset_and_set(0x11bc, 0xffffffff, 0x1e84800); MCHBAR16(0x11ca) = 0xfa; MCHBAR32(0x11e4) = 0x4e20; MCHBAR8(0x11bc) = 0xf; @@ -4078,8 +4078,8 @@ if ((deven & 8) && x2ca8 == 0) { MCHBAR16(0x1214) = 0x320; MCHBAR32(0x1600) = 0x40000000; - MCHBAR32_AND_OR(0x11f4, 0, 0x10000000); - MCHBAR16_AND_OR(0x1230, 0, 0x8000); + mchbar32_unset_and_set(0x11f4, 0xffffffff, 0x10000000); + mchbar16_unset_and_set(0x1230, 0xffff, 0x8000); MCHBAR32(0x1400) = 0x13040020; MCHBAR32(0x1404) = 0xe090120; MCHBAR32(0x1408) = 0x5120220; @@ -4176,14 +4176,14 @@ MCHBAR16(0x1220) = 0x1388; }
- MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!! + mchbar32_unset_and_set(0x2c80, 0xffffffff, 0x1053688); // !!!! MCHBAR32(0x1c04); // !!!! MCHBAR32(0x1804) = 0x406080;
MCHBAR8(0x2ca8);
if (x2ca8 == 0) { - MCHBAR8_AND(0x2ca8, ~3); + mchbar8_unset(0x2ca8, 3); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? /* This issues a CPU reset without resetting the platform */ printk(BIOS_DEBUG, "Issuing a CPU reset\n"); @@ -4192,12 +4192,12 @@ if (s3resume) write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (SLP_TYP_S3 << 10)); - MCHBAR32_OR(0x1af0, 0x10); + mchbar32_or(0x1af0, 0x10); halt(); }
MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); - MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! + mchbar32_unset_and_set(0x2c80, 0xffffffff, 0x53688); // !!!! pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220); MCHBAR16(0x2c20); // !!!! MCHBAR16(0x2c10); // !!!! @@ -4214,8 +4214,8 @@ MCHBAR16(0x616) = 0x26a; MCHBAR32(0x134) = 0x856000; MCHBAR32(0x160) = 0x5ffffff; - MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!! - MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!! + mchbar32_unset_and_set(0x114, 0xffffffff, 0xc2024440); // !!!! + mchbar32_unset_and_set(0x118, 0xffffffff, 0x4); // !!!! for (channel = 0; channel < NUM_CHANNELS; channel++) MCHBAR32(0x260 + (channel << 10)) = 0x30809ff | ((info.populated_ranks_mask[channel] & 3) << 20); @@ -4256,7 +4256,7 @@
program_base_timings(&info);
- MCHBAR8_OR(0x5ff, 0x80); + mchbar8_or(0x5ff, 0x80);
write_1d0(0x2, 0x1d5, 2, 1); write_1d0(0x20, 0x166, 7, 1); @@ -4304,9 +4304,9 @@ write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1); }
- MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!! + mchbar32_unset_and_set(0x1f4, 0xffffffff, 0x20000); // !!!! MCHBAR32(0x1f0) = 0x1d000200; - MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!! + mchbar8_unset_and_set(0x1f0, 0xff, 0x1); // !!!! MCHBAR8(0x1f0); // !!!!
program_board_delay(&info); @@ -4315,7 +4315,7 @@ MCHBAR8(0x5ff) = 0x80; MCHBAR8(0x5f4) = 0x1;
- MCHBAR32_AND(0x130, 0xfffffffd); // | 2 when ? + mchbar32_unset(0x130, 2); // | 2 when ? while (MCHBAR32(0x130) & 1) ; gav(read_1d0(0x14b, 7)); // = 0x81023100 @@ -4335,10 +4335,10 @@ write_1d0(0, 0xae, 6, 1); read_1d0(0x300, 4); // = 0x48088080 // !!!! write_1d0(0, 0x300, 6, 1); - MCHBAR16_AND_OR(0x356, 0, 0x1040); // !!!! - MCHBAR16_AND_OR(0x756, 0, 0x1040); // !!!! - MCHBAR32_AND(0x140, ~0x07000000); - MCHBAR32_AND(0x138, ~0x07000000); + mchbar16_unset_and_set(0x356, 0xffff, 0x1040); // !!!! + mchbar16_unset_and_set(0x756, 0xffff, 0x1040); // !!!! + mchbar32_unset(0x140, 0x07000000); + mchbar32_unset(0x138, 0x07000000); MCHBAR32(0x130) = 0x31111301; /* Wait until REG130b0 is 1. */ while (MCHBAR32(0x130) & 1) @@ -4404,13 +4404,13 @@ 1); write_500(&info, channel, 0x3, 0x69b, 2, 1); } - MCHBAR32_AND_OR(0x2d0, 0xff2c01ff, 0x200000); + mchbar32_unset_and_set(0x2d0, 0x00d3fe00, 0x200000); MCHBAR16(0x6c0) = 0x14a0; - MCHBAR32_AND_OR(0x6d0, 0xff0080ff, 0x8000); + mchbar32_unset_and_set(0x6d0, 0x00ff7f00, 0x8000); MCHBAR16(0x232) = 0x8; /* 0x40004 or 0 depending on ? */ - MCHBAR32_AND_OR(0x234, 0xfffbfffb, 0x40004); - MCHBAR32_AND_OR(0x34, 0xfffffffd, 5); + mchbar32_unset_and_set(0x234, 0x00040004, 0x40004); + mchbar32_unset_and_set(0x34, 0x00000002, 5); MCHBAR32(0x128) = 0x2150d05; MCHBAR8(0x12c) = 0x1f; MCHBAR8(0x12d) = 0x56; @@ -4422,10 +4422,10 @@ for (channel = 0; channel < NUM_CHANNELS; channel++) MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3) << 16; - MCHBAR32_AND_OR(0x134, 0xfc01ffff, 0x10000); - MCHBAR32_AND_OR(0x134, 0xfc85ffff, 0x850000); + mchbar32_unset_and_set(0x134, 0x03fe0000, 0x10000); + mchbar32_unset_and_set(0x134, 0x037a0000, 0x850000); for (channel = 0; channel < NUM_CHANNELS; channel++) - MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000, 0x8000000 | + mchbar32_unset_and_set(0x400*ch + 0x598, 0x18c00000, 0x8000000 | ((info.populated_ranks_mask[channel] & 3) << 20));
if (!s3resume) @@ -4443,8 +4443,8 @@
MCHBAR8(0x12c) = 0x9f;
- MCHBAR8_AND_OR(0x271, 0, 0xe); // 2 // !!!! - MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!! + mchbar8_unset_and_set(0x271, 0xff, 0xe); // 2 // !!!! + mchbar8_unset_and_set(0x671, 0xff, 0xe); // !!!!
if (!s3resume) { for (channel = 0; channel < NUM_CHANNELS; channel++) { @@ -4455,7 +4455,7 @@ (info.populated_ranks[channel][0][1] << 5); MCHBAR32(0x29c + (channel << 10)) = 0x77a; } - MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!! + mchbar32_unset_and_set(0x2c0, 0xffffffff, 0x6009cc00); // !!!!
{ u8 a, b; @@ -4492,7 +4492,7 @@ pci_write_config16(NORTHBRIDGE, 0xc8, 3); write_26c(0, 0x820); write_26c(1, 0x820); - MCHBAR32_OR(0x130, 2); + mchbar32_or(0x130, 2); /* end */
if (s3resume) { @@ -4504,10 +4504,10 @@ (info.populated_ranks[channel][0][1] << 5); MCHBAR32(0x29c + (channel << 10)) = 0x77a; } - MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!! + mchbar32_unset_and_set(0x2c0, 0xffffffff, 0x6009cc00); // !!!! }
- MCHBAR32_AND(0xfa4, ~0x01000002); + mchbar32_unset(0xfa4, 0x01000002); MCHBAR32(0xfb0) = 0x2000e019;
/* Before training. */ @@ -4533,20 +4533,20 @@ else MCHBAR8(0x111) = 0x20 | (3 << 2) | (1 << 6) | (0 << 7);
- MCHBAR32_AND(0xfac, ~0x80000000); + mchbar32_unset(0xfac, 0x80000000); MCHBAR32(0xfb4) = 0x4800; MCHBAR32(0xfb8) = (info.revision < 8) ? 0x20 : 0x0; MCHBAR32(0xe94) = 0x7ffff; MCHBAR32(0xfc0) = 0x80002040; MCHBAR32(0xfc4) = 0x701246; - MCHBAR8_AND(0xfc8, ~0x70); - MCHBAR32_OR(0xe5c, 0x1000000); - MCHBAR32_AND_OR(0x1a70, ~0x00100000, 0x00200000); + mchbar8_unset(0xfc8, 0x70); + mchbar32_or(0xe5c, 0x1000000); + mchbar32_unset_and_set(0x1a70, 0x00100000, 0x00200000); MCHBAR32(0x50) = 0x700b0; MCHBAR32(0x3c) = 0x10; MCHBAR8(0x1aa8) = (MCHBAR8(0x1aa8) & ~0x35) | 0xa; - MCHBAR8_OR(0xff4, 0x2); - MCHBAR32_AND_OR(0xff8, ~0xe008, 0x1020); + mchbar8_or(0xff4, 0x2); + mchbar32_unset_and_set(0xff8, 0xe008, 0x1020);
MCHBAR32(0xd00) = IOMMU_BASE2 | 1; MCHBAR32(0xd40) = IOMMU_BASE1 | 1; @@ -4560,28 +4560,28 @@ u32 eax;
eax = info.fsb_frequency / 9; - MCHBAR32_AND_OR(0xfcc, 0xfffc0000, + mchbar32_unset_and_set(0xfcc, 0x0003ffff, (eax * 0x280) | (eax * 0x5000) | eax | 0x40000); MCHBAR32(0x20) = 0x33001; }
for (channel = 0; channel < NUM_CHANNELS; channel++) { - MCHBAR32_AND(0x220 + (channel << 10), ~0x7770); + mchbar32_unset(0x220 + (channel << 10), 0x7770); if (info.max_slots_used_in_channel == 1) - MCHBAR16_OR(0x237 + (channel << 10), 0x0201); + mchbar16_or(0x237 + (channel << 10), 0x0201); else - MCHBAR16_AND(0x237 + (channel << 10), ~0x0201); + mchbar16_unset(0x237 + (channel << 10), 0x0201);
- MCHBAR8_OR(0x241 + (channel << 10), 1); + mchbar8_or(0x241 + (channel << 10), 1);
if (info.clock_speed_index <= 1 && (info.silicon_revision == 2 || info.silicon_revision == 3)) - MCHBAR32_OR(0x248 + (channel << 10), 0x00102000); + mchbar32_or(0x248 + (channel << 10), 0x00102000); else - MCHBAR32_AND(0x248 + (channel << 10), ~0x00102000); + mchbar32_unset(0x248 + (channel << 10), 0x00102000); }
- MCHBAR32_OR(0x115, 0x1000000); + mchbar32_or(0x115, 0x1000000);
{ u8 al; @@ -4605,7 +4605,7 @@ EPBAR32(EPVC1RCAP) = reg1c; // OK MCHBAR8(0xe08); // = 0x0 pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 - MCHBAR8_OR(0x1210, 2); + mchbar8_or(0x1210, 2); MCHBAR32(0x1200) = 0x8800440; MCHBAR32(0x1204) = 0x53ff0453; MCHBAR32(0x1208) = 0x19002043; @@ -4613,10 +4613,10 @@
if (info.revision == 0x10 || info.revision == 0x11) { MCHBAR16(0x1214) = 0x220; - MCHBAR8_OR(0x1210, 0x40); + mchbar8_or(0x1210, 0x40); }
- MCHBAR8_OR(0x1214, 0x4); + mchbar8_or(0x1214, 0x4); MCHBAR8(0x120c) = 0x1; MCHBAR8(0x1218) = 0x3; MCHBAR8(0x121a) = 0x3; @@ -4627,13 +4627,13 @@
/* revision dependent here. */
- MCHBAR16_OR(0x1230, 0x1f07); + mchbar16_or(0x1230, 0x1f07);
if (info.uma_enabled) - MCHBAR32_OR(0x11f4, 0x10000000); + mchbar32_or(0x11f4, 0x10000000);
- MCHBAR16_OR(0x1230, 0x8000); - MCHBAR8_OR(0x1214, 1); + mchbar16_or(0x1230, 0x8000); + mchbar8_or(0x1214, 1);
u8 bl, ebpb; u16 reg_1020; @@ -4663,7 +4663,7 @@
MCHBAR8(0x123e) = (MCHBAR8(0x123e) & 0xf) | 0x60; if (reg_1020 != 0) { - MCHBAR32_AND_OR(0x123c, ~0x00900000, 0x600000); + mchbar32_unset_and_set(0x123c, 0x00900000, 0x600000); MCHBAR8(0x101c) = 0xb8; }
@@ -4671,20 +4671,20 @@
if (info.uma_enabled) { u16 ax; - MCHBAR32_OR(0x11b0, 0x4000); - MCHBAR32_OR(0x11b4, 0x4000); - MCHBAR16_OR(0x1190, 0x4000); + mchbar32_or(0x11b0, 0x4000); + mchbar32_or(0x11b4, 0x4000); + mchbar16_or(0x1190, 0x4000);
ax = MCHBAR16(0x1190) & 0xf00; // = 0x480a // OK MCHBAR16(0x1170) = ax | (MCHBAR16(0x1170) & 0x107f) | 0x4080; - MCHBAR16_OR(0x1170, 0x1000); + mchbar16_or(0x1170, 0x1000);
udelay(1000);
u16 ecx; for (ecx = 0xffff; ecx && (MCHBAR16(0x1170) & 0x1000); ecx--) ; - MCHBAR16_AND(0x1190, ~0x4000); + mchbar16_unset(0x1190, 0x4000); }
pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2,