HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15542
-gerrit
commit b23896e67c864f42bf474ebf523c9f5d14a1302c Author: Elyes HAOUAS ehaouas@noos.fr Date: Sun Jul 3 18:00:21 2016 +0200
Intel/x4x correct DDR2 latency
Correct latency decode for DDR2.
Change-Id: I9d593b318fbd8f8a33de4deb3e0af93f7bd80c38 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/northbridge/intel/x4x/raminit.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 4f5575c..c62c2dd 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -36,7 +36,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
static void sdram_read_spds(struct sysinfo *s) { - u8 i, j, chan; + u8 i, j, chan, cas_bit; int status = 0; FOR_EACH_DIMM(i) { if (s->spd_map[i] == 0) { @@ -111,10 +111,13 @@ static void sdram_read_spds(struct sysinfo *s) s->dimms[i].chip_capacity = s->dimms[i].banks; s->dimms[i].rows = s->dimms[i].spd_data[3];// - 12; s->dimms[i].cols = s->dimms[i].spd_data[4];// - 9; - s->dimms[i].cas_latencies = 0x78; - s->dimms[i].cas_latencies &= s->dimms[i].spd_data[18]; - if (s->dimms[i].cas_latencies == 0) - s->dimms[i].cas_latencies = 7; + cas_bit = 2; + do { + if ((1 << cas_bit) & s->dimms[i].spd_data[18]) + break; + ++cas_bit; + } while (cas_bit < 0x8); + s->dimms[i].cas_latencies = cas_bit; s->dimms[i].tAAmin = s->dimms[i].spd_data[26]; s->dimms[i].tCKmin = s->dimms[i].spd_data[25]; s->dimms[i].width = (s->dimms[i].spd_data[13] >> 3) - 1;