Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG@12 PS5, Line 12: corresponding to available number of ways to 1b.
No, I meant: […]
Ok got it. I will work on this change.
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG@16 PS5, Line 16: =<Yet to run>
Needs update. […]
It is not yet verified on SKU with 4MB L3 cache. So I had kept the field as it is and thought to get it tested on this SKU.
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 413: %ecx
ecx was used to back up the number of ways in line 404. […]
Yes. I can back it up in edx and restore back after SF Mask programming.
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 415: $
%
Ack
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 427: IA32_CR_SF_QOS_MASK_2 with : * total number of LLC ways
The recommendation in the document Shyam shared was to set this to all 0s.
Ok. I will update this.