Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9513
-gerrit
commit 9941040e70a41a75b777a904cb6110d616260fba Author: Furquan Shaikh furquan@google.com Date: Tue Nov 11 11:18:59 2014 -0800
google/rush_ryu: Disable EC SW sync for proto boards before proto3
BUG=chrome-os-partner:33583 BRANCH=None TEST=No EC SW sync messages seen in depthcharge boot flow.
Change-Id: I62b7061a833ba607457a580fb2b217b9c2df0e74 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 552b1d19bacd6692ffb6257fc81220ba0ed89344 Original-Change-Id: I5c1df5a23977f461011a2937adda5770b4742378 Original-Signed-off-by: Furquan Shaikh furquan@google.com Original-Reviewed-on: https://chromium-review.googlesource.com/229081 Original-Tested-by: Furquan Shaikh furquan@chromium.org Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Commit-Queue: Furquan Shaikh furquan@chromium.org --- src/mainboard/google/rush_ryu/mainboard.c | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 1a78e02..9ad7f77 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -18,7 +18,9 @@ */
#include <arch/mmu.h> +#include <boardid.h> #include <boot/coreboot_tables.h> +#include <cbmem.h> #include <device/device.h> #include <elog.h> #include <memrange.h> @@ -29,6 +31,13 @@ #include <soc/nvidia/tegra/i2c.h> #include <soc/padconfig.h> #include <vendorcode/google/chromeos/chromeos.h> +#if IS_ENABLED(CONFIG_CHROMEOS) +#include <vboot_struct.h> +#include <vendorcode/google/chromeos/vboot_handoff.h> +#include <vendorcode/google/chromeos/vboot2/misc.h> +#endif + +#include "gpio.h"
static const struct pad_config mmcpads[] = { /* MMC4 (eMMC) */ @@ -58,6 +67,27 @@ static const struct funit_cfg funits[] = { FUNIT_CFG_USB(USBD), };
+/* HACK: For proto boards before proto3, we want to disable ec sw sync */ +static void fix_ec_sw_sync(void) +{ +#if IS_ENABLED(CONFIG_CHROMEOS) + struct vboot_handoff *vh; + + if (board_id() >= BOARD_ID_PROTO_3) + return; + + vh = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + + if (vh == NULL) { + printk(BIOS_ERR, "No vboot handoff struct found\n"); + return; + } + + VbSharedDataHeader *vb_sd = (VbSharedDataHeader *)vh->shared_data; + vb_sd->flags &= ~VBSD_EC_SOFTWARE_SYNC; +#endif +} + static void mainboard_init(device_t dev) { /* PLLD should be 2 * pixel clock (301620khz). */ @@ -76,6 +106,8 @@ static void mainboard_init(device_t dev) i2c_init(I2C6_BUS); elog_init(); elog_add_boot_reason(); + + fix_ec_sw_sync(); }
static void mainboard_enable(device_t dev)