Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42440 )
Change subject: soc/intel/cannonlake: Add PchPmPwrCycDur to chip options
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Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch...
File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/ch...
PS3, Line 321: uint8_t PchPmPwrCycDur;
`src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h` says that 0 is the default. […]
As per EDS, only few values are really supported. I believe the default here means that if this UPD is left as 0, then FSP configures it as 4 seconds by default.
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/fs...
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42440/3/src/soc/intel/cannonlake/fs...
PS3, Line 415: PchPmPwrCycDur
You will need a check to ensure that this is not lesser than the other assertion widths as recommended by the EDS.
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