[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44557 )

Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
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Patch Set 1:

It looks like we're falling into copy-and-paste again, this code was originally developed for cannon lake, it was copied to jasper lake as well. Could we consider moving this to soc/intel/common/block/pmc instead of having a 3rd copy floating around?