[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne/chipset.cb: rename alias for SATA controllers

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51190 )

Change subject: soc/amd/cezanne/chipset.cb: rename alias for SATA controllers
......................................................................

soc/amd/cezanne/chipset.cb: rename alias for SATA controllers

Renoir/Cezanne have two SATA controllers with 2 ports each, so call them
sata_0 and sata_1.

Signed-off-by: Felix Held 
Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5
---
M src/soc/amd/cezanne/chipset.cb
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/51190/1

diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb
index e82d435..5e3d269 100644
--- a/src/soc/amd/cezanne/chipset.cb
+++ b/src/soc/amd/cezanne/chipset.cb
@@ -32,8 +32,8 @@
    		device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
    	end
    	device pci 8.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
-			device pci 0.0 alias sata_ahci off end # SATA AHCI Mode
-			device pci 0.1 alias sata_raid off end # SATA Controller; SATA Raid/AHCI Mode
+			device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode
+			device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode
    		device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
    		device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
    	end