[coreboot-gerrit] Change in ...coreboot[master]: google/kukui: boot up sspm

[Julius Werner (Code Review)]

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31516 )

Change subject: google/kukui: boot up sspm
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/31516/1/src/mainboard/google/kukui/mainboard... 
File src/mainboard/google/kukui/mainboard.c:

https://review.coreboot.org/#/c/31516/1/src/mainboard/google/kukui/mainboard... 
PS1, Line 44: unsigned char buf[BUF_SIZE];
> SSPM_SRAM_BASE is accessed through APB box. It can't support byte access only supports word access. […]

Can you map the area as cacheable? That might prevent that problem because the cache will combine writes. Caching is also important for decompression speed (because the decompression algorithm does many back-references to already decompressed parts).

If you can only map it as device memory, then yeah, you'll probably not get around a static bounce buffer here. It shouldn't be a huge deal because ramstage size is usually not limited. (I'd hide all of that in a separate file then, though... in fact, why is any of this called from mainboard.c? Can't you put it in soc.c?)