Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76076?usp=email )
Change subject: mb/google/rex: Avoid LPDDR5/x hang ......................................................................
mb/google/rex: Avoid LPDDR5/x hang
This patch avoids hang observed on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s.
As per Intel doc 769410 the expected work around is to change SAGV point 0 from 2133 G4 to 3200 G4.
BUG=b:287170545 TEST=Able to perform 500 power cycles on google/rex without any hang.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I02a9cadc075f396549703d7a008382e76268f865 --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/76076/1
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 5297ce2..0d639e3 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -41,7 +41,7 @@
register "sagv" = "SAGV_ENABLED"
- register "sagv_freq_mhz[0]" = "2133" + register "sagv_freq_mhz[0]" = "3200" register "sagv_gear[0]" = "4"
register "sagv_freq_mhz[1]" = "6000"