Alexander Couzens (lynxis@fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9250
-gerrit
commit 6e2004855a49ef20464c3d0f01126e8f57a1776f Author: Alexander Couzens lynxis@fe80.eu Date: Thu Apr 2 23:12:50 2015 +0200
device_t: remove all reference of device_t in SMM, PRE_RAM, ROM_CC
device_t is a type which should only used in RAM stage. This also removes a x86 workaround which defined it to a dev_pcifn_t compatible type.
Change-Id: Ied65fdab548d2477c284642663fd72c530608cd2 Signed-off-by: Alexander Couzens lynxis@fe80.eu --- src/arch/x86/include/arch/io.h | 4 -- src/cpu/amd/model_10xxx/fidvid.c | 28 ++++++------- src/cpu/amd/model_10xxx/init_cpus.c | 2 +- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/include/cpu/amd/model_fxx_rev.h | 6 +-- src/include/device/device.h | 2 +- src/include/device/pci.h | 6 +-- src/lib/debug.c | 4 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/kfsn4-dre/romstage.c | 4 +- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 4 +- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/getac/p470/romstage.c | 8 ++-- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 2 +- src/mainboard/intel/cougar_canyon2/romstage.c | 2 +- src/mainboard/intel/d810e2cb/gpio.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 6 +-- src/mainboard/kontron/ktqm77/romstage.c | 6 +-- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/rca/rm4100/gpio.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 8 ++-- src/mainboard/roda/rk9/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 4 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 +- src/mainboard/technexion/tim5690/tn_post_code.c | 4 +- src/mainboard/thomson/ip1000/gpio.c | 2 +- src/mainboard/tyan/s8226/BiosCallOuts.c | 4 +- src/mainboard/tyan/s8226/romstage.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 8 ++-- src/mainboard/via/vt8454c/romstage.c | 2 +- src/northbridge/amd/agesa/family10/reset_test.h | 4 +- src/northbridge/amd/amdfam10/amdfam10.h | 6 +-- src/northbridge/amd/amdfam10/debug.c | 8 ++-- src/northbridge/amd/amdfam10/early_ht.c | 2 +- src/northbridge/amd/amdfam10/pci.c | 8 ++-- src/northbridge/amd/amdfam10/raminit.h | 4 +- src/northbridge/amd/amdfam10/setup_resource_map.c | 8 ++-- src/northbridge/amd/amdht/ht_wrapper.c | 2 +- src/northbridge/amd/amdk8/amdk8.h | 2 +- src/northbridge/amd/amdk8/coherent_ht.c | 10 ++--- src/northbridge/amd/amdk8/debug.c | 8 ++-- src/northbridge/amd/amdk8/early_ht.c | 4 +- src/northbridge/amd/amdk8/f.h | 4 +- src/northbridge/amd/amdk8/f_pci.c | 8 ++-- src/northbridge/amd/amdk8/incoherent_ht.c | 34 ++++++++-------- src/northbridge/amd/amdk8/pre_f.h | 4 +- src/northbridge/amd/amdk8/raminit.c | 8 ++-- src/northbridge/amd/amdk8/raminit.h | 2 +- src/northbridge/amd/amdk8/raminit_f.c | 8 ++-- src/northbridge/amd/amdk8/setup_resource_map.c | 4 +- src/northbridge/amd/lx/northbridge.h | 2 +- src/northbridge/intel/e7501/debug.c | 6 +-- src/northbridge/intel/e7501/raminit.h | 2 +- src/northbridge/intel/e7505/debug.c | 6 +-- src/northbridge/intel/e7505/raminit.h | 2 +- src/northbridge/intel/gm45/early_init.c | 2 +- src/northbridge/intel/gm45/igd.c | 12 +++--- src/northbridge/intel/gm45/iommu.c | 4 +- src/northbridge/intel/gm45/pcie.c | 8 ++-- src/northbridge/intel/i3100/raminit.c | 2 +- src/northbridge/intel/i3100/raminit.h | 2 +- src/northbridge/intel/i3100/raminit_ep80579.c | 2 +- src/northbridge/intel/i3100/raminit_ep80579.h | 2 +- src/northbridge/intel/i5000/raminit.c | 34 ++++++++-------- src/northbridge/intel/i5000/raminit.h | 2 +- src/northbridge/intel/i855/debug.c | 4 +- src/northbridge/intel/i945/debug.c | 4 +- src/northbridge/intel/nehalem/acpi.c | 2 +- src/northbridge/intel/nehalem/raminit.c | 2 +- src/northbridge/via/cn700/raminit.c | 8 ++-- src/northbridge/via/cn700/raminit.h | 2 +- src/northbridge/via/cx700/early_smbus.c | 2 +- src/northbridge/via/cx700/raminit.c | 2 +- src/northbridge/via/vx800/early_smbus.c | 2 +- src/northbridge/via/vx800/pci_rawops.h | 4 +- src/northbridge/via/vx800/uma_ram_setting.c | 2 +- src/northbridge/via/vx900/early_smbus.c | 2 +- src/northbridge/via/vx900/vx900.h | 8 ++-- src/southbridge/amd/amd8111/amd8111.h | 10 +++-- src/southbridge/amd/amd8111/early_ctrl.c | 8 ++-- src/southbridge/amd/amd8111/early_smbus.c | 2 +- src/southbridge/amd/cimx/sb700/early.c | 6 +-- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/rs690/early_setup.c | 44 ++++++++++----------- src/southbridge/amd/rs780/early_setup.c | 48 +++++++++++------------ src/southbridge/amd/sb600/early_setup.c | 14 +++---- src/southbridge/amd/sb600/sb600.h | 4 ++ src/southbridge/amd/sb700/early_setup.c | 18 ++++----- src/southbridge/amd/sb700/sb700.h | 5 ++- src/southbridge/amd/sb800/early_setup.c | 14 +++---- src/southbridge/amd/sb800/sb800.h | 9 +++-- src/southbridge/broadcom/bcm5785/early_setup.c | 10 ++--- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/intel/bd82x6x/early_smbus.c | 2 +- src/southbridge/intel/bd82x6x/early_thermal.c | 2 +- src/southbridge/intel/bd82x6x/early_usb.c | 4 +- src/southbridge/intel/bd82x6x/pch.c | 6 ++- src/southbridge/intel/bd82x6x/pch.h | 21 ++++++---- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/fsp_bd82x6x/early_smbus.c | 2 +- src/southbridge/intel/fsp_bd82x6x/early_usb.c | 4 +- src/southbridge/intel/fsp_bd82x6x/pch.h | 6 ++- src/southbridge/intel/fsp_rangeley/early_smbus.c | 2 +- src/southbridge/intel/fsp_rangeley/early_usb.c | 2 +- src/southbridge/intel/i3100/early_lpc.c | 4 +- src/southbridge/intel/i3100/early_smbus.c | 2 +- src/southbridge/intel/i3100/i3100.h | 5 +++ src/southbridge/intel/i82371eb/early_pm.c | 2 +- src/southbridge/intel/i82371eb/early_smbus.c | 2 +- src/southbridge/intel/i82801ax/early_smbus.c | 2 +- src/southbridge/intel/i82801bx/early_smbus.c | 2 +- src/southbridge/intel/i82801dx/early_smbus.c | 2 +- src/southbridge/intel/i82801dx/i82801dx.h | 9 +++-- src/southbridge/intel/i82801dx/smihandler.c | 2 +- src/southbridge/intel/i82801dx/tco_timer.c | 2 +- src/southbridge/intel/i82801ex/early_smbus.c | 2 +- src/southbridge/intel/i82801gx/early_smbus.c | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 14 +++++-- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/i82801ix/early_init.c | 2 +- src/southbridge/intel/i82801ix/early_smbus.c | 2 +- src/southbridge/intel/ibexpeak/early_smbus.c | 2 +- src/southbridge/intel/ibexpeak/early_thermal.c | 2 +- src/southbridge/intel/ibexpeak/pch.h | 1 + src/southbridge/intel/ibexpeak/smi.c | 4 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- src/southbridge/intel/lynxpoint/early_smbus.c | 2 +- src/southbridge/intel/lynxpoint/early_usb.c | 2 +- src/southbridge/intel/lynxpoint/pch.h | 17 +++++--- src/southbridge/nvidia/ck804/early_setup_car.c | 2 +- src/southbridge/nvidia/ck804/early_smbus.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/early_setup_car.c | 4 +- src/southbridge/nvidia/mcp55/early_smbus.c | 2 +- src/southbridge/sis/sis966/early_ctrl.c | 2 +- src/southbridge/via/vt8237r/early_smbus.c | 16 ++++---- 146 files changed, 415 insertions(+), 380 deletions(-)
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 3130f64..bba58dd 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -222,10 +222,6 @@ static inline int log2f(int value)
#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
-/* FIXME: Sources for romstage still use device_t. */ -/* Use pci_devfn_t or pnp_devfn_t instead */ -typedef u32 device_t; - /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 798d538..aedfbae 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -125,7 +125,7 @@ static void enable_fid_change(u8 fid) { u32 dword; u32 nodes; - device_t dev; + pci_devfn_t dev; int i;
nodes = get_nodes(); @@ -142,7 +142,7 @@ static void enable_fid_change(u8 fid) } }
-static void applyBoostFIDOffset( device_t dev ) { +static void applyBoostFIDOffset( pci_devfn_t dev ) { // BKDG 2.4.2.8 // revision E only, but E is apparently not supported yet, therefore untested if ((cpuid_edx(0x80000007) & CPB_MASK) @@ -159,7 +159,7 @@ static void applyBoostFIDOffset( device_t dev ) { } }
-static void enableNbPState1( device_t dev ) { +static void enableNbPState1( pci_devfn_t dev ) { u32 cpuRev = mctGetLogicalCPUID(0xFF); if (cpuRev & AMD_FAM10_C3) { u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); @@ -179,7 +179,7 @@ static void enableNbPState1( device_t dev ) { } }
-static u8 setPStateMaxVal( device_t dev ) { +static u8 setPStateMaxVal( pci_devfn_t dev ) { u8 i,maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); @@ -199,7 +199,7 @@ static u8 setPStateMaxVal( device_t dev ) { return maxpstate; }
-static void dualPlaneOnly( device_t dev ) { +static void dualPlaneOnly( pci_devfn_t dev ) { // BKDG 2.4.2.7
u32 cpuRev = mctGetLogicalCPUID(0xFF); @@ -243,7 +243,7 @@ static int vidTo100uV(u8 vid) return voltage; }
-static void setVSRamp(device_t dev) { +static void setVSRamp(pci_devfn_t dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] * If this field accepts 8 values between 10 and 500 us why * does page 324 say "BIOS should set this field to 001b." @@ -258,7 +258,7 @@ static void setVSRamp(device_t dev) { pci_write_config32(dev, 0xd8, dword); }
-static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev) { u8 pviModeFlag; u8 highVoltageVid, lowVoltageVid, bValue; @@ -434,7 +434,7 @@ static u32 power_up_down(int node, u8 procPkg) { }
static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { - device_t dev = NODE_PCI(node, 3); + pci_devfn_t dev = NODE_PCI(node, 3);
/* Program fields in Clock Power/Control register0 (F3xD4) */
@@ -458,7 +458,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
}
-static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { +static void config_power_ctrl_misc_reg(pci_devfn_t dev, u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xA0);
@@ -491,7 +491,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { pci_write_config32(dev, 0xA0, dword); }
-static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { +static void config_nb_syn_ptr_adj(pci_devfn_t dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ @@ -513,7 +513,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { pci_write_config32(dev, 0xdc, dword); }
-static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { +static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, u32 cpuRev, u8 procPkg) { /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ u32 dword; u32 c1= 1; @@ -573,7 +573,7 @@ static void prep_fid_change(void) { u32 dword; u32 nodes; - device_t dev; + pci_devfn_t dev; int i;
/* This needs to be run before any Pstate changes are requested */ @@ -776,7 +776,7 @@ static u32 needs_NB_COF_VID_update(void)
static u32 init_fidvid_core(u32 nodeid, u32 coreid) { - device_t dev; + pci_devfn_t dev; u32 vid_max; u32 fid_max = 0; u8 nb_cof_vid_update = needs_NB_COF_VID_update(); @@ -937,7 +937,7 @@ static void finalPstateChange(void) static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; - device_t dev; + pci_devfn_t dev; u32 reg1fc; u32 dtemp; u32 nbvid; diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 10c0c8a..1d8d76b 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -362,7 +362,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_ColdR_Detect; diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 12d3a95..05cfa91 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -310,7 +310,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_INIT_Detect; diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 7cd6158..7e1d3ed 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -77,7 +77,7 @@ static inline int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,2); val_old = pci_read_config32(dev, 0x80); val = val_old; @@ -95,7 +95,7 @@ static inline int is_e0_later_in_bsp(int nodeid) static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 0; dev = PCI_DEV(0, 0x18+nodeid, 3); @@ -106,7 +106,7 @@ static inline int is_cpu_f0_in_bsp(int nodeid) static inline int is_cpu_pre_f2_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 1; dev = PCI_DEV(0, 0x18+nodeid, 3); diff --git a/src/include/device/device.h b/src/include/device/device.h index c1c9fdb..af3d52e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -15,9 +15,9 @@ #include <device/path.h>
struct device; +typedef struct device * device_t;
#ifndef __SIMPLE_DEVICE__ -typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 4e712f9..174f1a7 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -103,13 +103,13 @@ static inline const struct pci_operations *ops_pci(device_t dev)
#endif /* ! __SIMPLE_DEVICE__ */
-#ifdef __PRE_RAM__ +#if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__) unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); -#else /* !__PRE_RAM__ */ +#else /* !__PRE_RAM__ && !__SMM__ && !__ROMCC__ */ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); -#endif /* __PRE_RAM__ */ +#endif /* __PRE_RAM__ || __SMM__ || __ROMCC__ */
void pci_early_bridge_init(void); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); diff --git a/src/lib/debug.c b/src/lib/debug.c index 8d629c2..e6cb4fa 100644 --- a/src/lib/debug.c +++ b/src/lib/debug.c @@ -27,7 +27,7 @@ static void print_debug_pci_dev(unsigned dev)
static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0x00, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { u32 id; @@ -61,7 +61,7 @@ static void dump_pci_device(unsigned dev)
static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { u32 id; diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 6e099b3..927cecb 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -88,7 +88,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 61e27d0..624ac9a 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -88,7 +88,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 048da22..e6c110c 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -86,7 +86,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 9680174..bf8a6cf 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -95,7 +95,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) */ unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); @@ -146,7 +146,7 @@ static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit
for (i = 0; i < 4; i++) { u32 id; - device_t dev; + pci_devfn_t dev; if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, bus_unit_id, 0); else diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 4391aa0..6b62a87 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -72,7 +72,7 @@ static void sio_setup(void) { u8 byte; u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ + pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
/* Subject decoding */ byte = pci_read_config8(dev, 0x7b); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 93b9202..9f1e0cf 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -105,7 +105,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index bfc3db0..f888a21 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -89,7 +89,7 @@ void soft_reset(void)
unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); @@ -187,7 +187,7 @@ static void m2v_it8712f_gpio_init(void)
static void m2v_bus_init(void) { - device_t dev; + pci_devfn_t dev;
printk(BIOS_SPEW, "m2v_bus_init\n");
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 667360a..8e26e65 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -46,7 +46,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index c4b053f..ac059ee 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -106,19 +106,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pci_devfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); }
-static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pci_devfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); }
-static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pci_devfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -127,7 +127,7 @@ static void pnp_write_register(device_t dev, int reg, int val)
static void early_superio_config(void) { - device_t dev; + pci_devfn_t dev;
dev=PNP_DEV(0x4e, 0x00);
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index a1515ee..b175d86 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -37,7 +37,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h>
-static void it8728f_b75md3h_disable_reboot(device_t dev) +static void it8728f_b75md3h_disable_reboot(pci_devfn_t dev) { /* GPIO SIO settings */ ite_reg_write(dev, 0xEF, 0x7E); // magic diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index ece65d8..3d8dc38 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -77,7 +77,7 @@ static void ich7_enable_lpc(void) */ static void early_superio_config_w83627ehg(void) { - device_t dev; + pci_devfn_t dev;
dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev); diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index 04e7bd0..0e5c401 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -68,7 +68,7 @@ void main(unsigned long bist) console_init();
/* Enable COM3. */ - device_t dev = PNP_DEV(0x2e, 0x0b); + pci_devfn_t dev = PNP_DEV(0x2e, 0x0b); u16 port = dev >> 8; outb(0x55, port); pnp_set_logical_device(dev); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 8a96d3b..58aa0c6 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -55,7 +55,7 @@ static inline void reset_system(void)
static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/intel/d810e2cb/gpio.c b/src/mainboard/intel/d810e2cb/gpio.c index a95fc9a..3aa1f1e 100644 --- a/src/mainboard/intel/d810e2cb/gpio.c +++ b/src/mainboard/intel/d810e2cb/gpio.c @@ -24,7 +24,7 @@ /* Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) { - device_t dev; + pci_devfn_t dev; uint16_t port;
/* Southbridge GPIOs. */ diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 45d92d8..151a8c4 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -48,7 +48,7 @@
static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV;
/* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 8a17113..fa93c5d0 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -50,7 +50,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index e72c3dc..bb20bdc 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -79,14 +79,14 @@ static void ich7_enable_lpc(void) }
/* TODO: superio code should really not be in mainboard */ -static void pnp_enter_func_mode(device_t dev) +static void pnp_enter_func_mode(pci_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); }
-static void pnp_exit_func_mode(device_t dev) +static void pnp_exit_func_mode(pci_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -99,7 +99,7 @@ static void pnp_exit_func_mode(device_t dev) */ static void early_superio_config_w83627thg(void) { - device_t dev; + pci_devfn_t dev;
dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev); diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 22dc33d..effd740 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -70,14 +70,14 @@ static void rcba_config(void) RCBA32(FD) = reg32; }
-static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pci_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); }
-static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pci_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -87,7 +87,7 @@ static void superio_gpio_config(void) { int lvds_3v = 0; // 0 (5V) or 1 (3V3) int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled - device_t dev = PNP_DEV(0x2e, 0x9); + pci_devfn_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 094e1dc..7df849e 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -99,7 +99,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pci_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0xa0);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index b997637..cd456e8 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -106,7 +106,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pci_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0x06);
diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c index 0527b68..98e5613 100644 --- a/src/mainboard/rca/rm4100/gpio.c +++ b/src/mainboard/rca/rm4100/gpio.c @@ -25,7 +25,7 @@ /* Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) { - device_t dev; + pci_devfn_t dev; uint16_t port; uint32_t set_gpio;
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index a7fd007..91218e4 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -94,19 +94,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static inline void pnp_enter_ext_func_mode(device_t dev) +static inline void pnp_enter_ext_func_mode(pci_devfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); }
-static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pci_devfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); }
-static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pci_devfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -115,7 +115,7 @@ static void pnp_write_register(device_t dev, int reg, int val)
static void early_superio_config(void) { - device_t dev; + pci_devfn_t dev;
dev=PNP_DEV(0x2e, 0x00);
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index c8b75e0..236530a 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -88,7 +88,7 @@ static void default_superio_gpio_setup(void) GP1 GP2 GP3 GP4 fd 17 88 14 */ - const device_t sio = PNP_DEV(0x2e, 0); + const pci_devfn_t sio = PNP_DEV(0x2e, 0);
/* Enter super-io's configuration state. */ pnp_enter_conf_state(sio); diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 6fc0154..65ba5d8 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -43,7 +43,7 @@
static UINT8 select_socket(UINT8 socket_id) { - device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus + pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus UINT8 value = 0; UINT8 gpio56_to_53 = 0;
@@ -66,7 +66,7 @@ static UINT8 select_socket(UINT8 socket_id)
static void restore_socket(UINT8 original_value) { - device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus + pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, original_value); } #endif diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 8583f2a..4bc06c4 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -117,14 +117,14 @@ static const u8 spd_addr[] = { #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
/* TODO: superio code should really not be in mainboard */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pci_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); }
-static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pci_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/mainboard/technexion/tim5690/tn_post_code.c b/src/mainboard/technexion/tim5690/tn_post_code.c index 422627e..d1a9c23 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.c +++ b/src/mainboard/technexion/tim5690/tn_post_code.c @@ -40,7 +40,7 @@ void technexion_post_code_init(void) { uint8_t reg8_data; - device_t dev=0; + pci_devfn_t dev=0;
// SMBus Module and ACPI Block (Device 20, Function 0) dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM), 0); @@ -133,7 +133,7 @@ void technexion_post_code_init(void) void technexion_post_code(uint8_t udata8) { uint8_t u8_data; - device_t dev=0; + pci_devfn_t dev=0;
// SMBus Module and ACPI Block (Device 20, Function 0) #ifdef __PRE_RAM__ diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c index bcb02bc..e7f6157 100644 --- a/src/mainboard/thomson/ip1000/gpio.c +++ b/src/mainboard/thomson/ip1000/gpio.c @@ -25,7 +25,7 @@ /* Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) { - device_t dev; + pci_devfn_t dev; uint16_t port; uint32_t set_gpio;
diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index d31b696..e02bd40 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -40,7 +40,7 @@
static UINT8 select_socket(UINT8 socket_id) { - device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS + pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS UINT8 value = 0; UINT8 gpio52_to_49 = 0;
@@ -72,7 +72,7 @@ static UINT8 select_socket(UINT8 socket_id)
static void restore_socket(UINT8 original_value) { - device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS + pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, original_value);
// TODO: Restore previous GPIO48 configurations? diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index d57d27d..790972a 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -47,7 +47,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x31);
/* For serial port. */ - device_t dev = PCI_DEV(0, 0x14, 3); + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
/* Halt if there was a built in self test failure */ diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index e93d26b..93b50b9 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -43,7 +43,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 174f430..be30028 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -54,7 +54,7 @@ */ static int acpi_is_wakeup_early_via_vx800(void) { - device_t dev; + pci_devfn_t dev; u16 tmp, result;
printk(BIOS_DEBUG, "In acpi_is_wakeup_early_via_vx800\n"); @@ -80,7 +80,7 @@ static int acpi_is_wakeup_early_via_vx800(void) /* All content of this function came from the cx700 port of coreboot. */ static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; #if 0 /* * Add and close this switch, since some line cause error, some @@ -375,8 +375,8 @@ void main(unsigned long bist) { u16 boot_mode; u8 rambits, Data8, Data; - device_t device; - /* device_t dev; */ + pci_devfn_t device; + /* pci_devfn_t dev; */
/* * Enable multifunction for northbridge. These 4 lines (until diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 5a74255..e3cb87e 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -38,7 +38,7 @@
static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h index 8c8d9a0..a38cde8 100644 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -33,7 +33,7 @@ static inline u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -42,7 +42,7 @@ static inline u32 warm_reset_detect(u8 nodeid) static inline void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 238c45f..47a7476 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -985,10 +985,10 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #endif
struct link_pair_t { - device_t udev; + pci_devfn_t udev; u32 upos; u32 uoffs; - device_t dev; + pci_devfn_t dev; u32 pos; u32 offs; u8 host; @@ -1050,7 +1050,7 @@ device_t get_node_pci(u32 nodeid, u32 fn); #endif
#ifdef __PRE_RAM__ -void showallroutes(int level, device_t dev); +void showallroutes(int level, pci_devfn_t dev);
void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base); diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 6aed390..64ea892 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -38,7 +38,7 @@ static void print_debug_pci_dev(u32 dev)
static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -63,7 +63,7 @@ static inline void print_pci_devices(void)
static inline void print_pci_devices_on_bus(u32 busn) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -164,7 +164,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -189,7 +189,7 @@ static inline void dump_pci_devices(void)
static inline void dump_pci_devices_on_bus(u32 busn) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 1a1f34c..5b31118 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -97,7 +97,7 @@ static void enumerate_ht_chain(void) if ((flags >> 13) == 0) { unsigned count; unsigned ctrl, ctrl_off; - device_t devx; + pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(next_unitid>=0x18) { diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c index 061359e..5387ae0 100644 --- a/src/northbridge/amd/amdfam10/pci.c +++ b/src/northbridge/amd/amdfam10/pci.c @@ -23,7 +23,7 @@ /* bit [10,8] are dev func, bit[1,0] are dev index */
-static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index) +static u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index) { u32 dword;
@@ -33,7 +33,7 @@ static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index) }
#ifdef UNUSED_CODE -static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data) +static void pci_write_config32_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) {
pci_write_config32(dev, index_reg, index); @@ -43,7 +43,7 @@ static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 } #endif
-static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index) +static u32 pci_read_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index) {
u32 dword; @@ -58,7 +58,7 @@ static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index) }
#ifdef UNUSED_CODE -static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data) +static void pci_write_config32_index_wait(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) {
u32 dword; diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 8ecdac3..84cb47d 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -27,7 +27,7 @@ #define DIMM_SOCKETS 8 struct mem_controller { u32 node_id; - device_t f0, f1, f2, f3, f4, f5; + pci_devfn_t f0, f1, f2, f3, f4, f5; /* channelA, channelB belong to DCT0, * channelC, channelD belong to DCT1 * Each DCT may support one ganged logical FBDIMM ---> 128 bit @@ -51,7 +51,7 @@ struct mem_controller { #define DIMM_SOCKETS 4 struct mem_controller { u32 node_id; - device_t f0, f1, f2, f3, f4, f5; + pci_devfn_t f0, f1, f2, f3, f4, f5; /* channel0 is DCT0 --- channelA * channel1 is DCT1 --- channelB * can be ganged, a single dual-channel DCT ---> 128 bit diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index b8a0923..a08082b 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -27,7 +27,7 @@ static void setup_resource_map(const u32 *register_values, u32 max) // printk(BIOS_DEBUG, "setting up resource map....");
for(i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg;
@@ -47,7 +47,7 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p u32 i; // printk(BIOS_DEBUG, "setting up resource map offset...."); for(i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; u32 where; unsigned long reg; dev = (register_values[i] & ~0xfff) + offset_pci_dev; @@ -83,7 +83,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset switch (register_values[i]) { case RES_PCI_IO: //PCI { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg; dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; @@ -151,7 +151,7 @@ void setup_resource_map_x(const u32 *register_values, u32 max) switch (register_values[i]) { case RES_PCI_IO: //PCI { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg; dev = register_values[i+1] & ~0xff; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index a38caa4..7f8297f 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -71,7 +71,7 @@
static u32 get_nodes(void) { - device_t dev; + pci_devfn_t dev; u32 nodes;
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 05117f7..2992abc 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -12,7 +12,7 @@ #endif
#ifdef __PRE_RAM__ -void showallroutes(int level, device_t dev); +void showallroutes(int level, pci_devfn_t dev); void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base); void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); #endif diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index a8d8700..134e9ad 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -273,7 +273,7 @@ static int verify_connection(u8 dest) return 1; }
-static uint16_t read_freq_cap(device_t dev, uint8_t pos) +static uint16_t read_freq_cap(pci_devfn_t dev, uint8_t pos) { /* Handle bugs in valid hypertransport frequency reporting */ uint16_t freq_cap; @@ -301,7 +301,7 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos) return freq_cap; }
-static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2) +static int optimize_connection(pci_devfn_t node1, uint8_t link1, pci_devfn_t node2, uint8_t link2) { static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; @@ -1616,7 +1616,7 @@ static void coherent_ht_finalize(unsigned nodes) rev_a0 = is_cpu_rev_a0(); #endif for (node = 0; node < nodes; node++) { - device_t dev; + pci_devfn_t dev; uint32_t val; dev = NODE_HT(node);
@@ -1660,7 +1660,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) unsigned node; int needs_reset = 0; for(node = 0; node < nodes; node++) { - device_t dev; + pci_devfn_t dev; uint32_t cmd; dev = NODE_MC(node); #if !CONFIG_K8_REV_F_SUPPORT @@ -1730,7 +1730,7 @@ static int optimize_link_read_pointers(unsigned nodes) unsigned node; int needs_reset = 0; for(node = 0; node < nodes; node++) { - device_t f0_dev, f3_dev; + pci_devfn_t f0_dev, f3_dev; uint32_t cmd_ref, cmd; int link; f0_dev = NODE_HT(node); diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index c1021e5..bd755d3 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -18,7 +18,7 @@ static void print_debug_pci_dev(unsigned dev)
static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -58,7 +58,7 @@ static void dump_pci_device(unsigned dev) }
#if CONFIG_K8_REV_F_SUPPORT -static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); +static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, uint32_t index_reg, uint32_t index); static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { int i; @@ -82,7 +82,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -107,7 +107,7 @@ static inline void dump_pci_devices(void)
static inline void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 6449f4b..edd436e 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -13,7 +13,7 @@ static void enumerate_ht_chain(void) * links needs to be programed to point at bus 0. */ unsigned next_unitid, last_unitid; - device_t dev; + pci_devfn_t dev; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid = 0; @@ -61,7 +61,7 @@ static void enumerate_ht_chain(void) if ((flags >> 13) == 0) { unsigned count; unsigned ctrl, ctrl_off; - device_t devx; + pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index 4f958c5..baa6b10 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -486,10 +486,10 @@ struct mem_info { // pernode } __attribute__((packed));
struct link_pair_st { - device_t udev; + pci_devfn_t udev; uint32_t upos; uint32_t uoffs; - device_t dev; + pci_devfn_t dev; uint32_t pos; uint32_t offs;
diff --git a/src/northbridge/amd/amdk8/f_pci.c b/src/northbridge/amd/amdk8/f_pci.c index d89dadc..928fdc4 100644 --- a/src/northbridge/amd/amdk8/f_pci.c +++ b/src/northbridge/amd/amdk8/f_pci.c @@ -3,7 +3,7 @@
#ifdef UNUSED_CODE /* bit [10,8] are dev func, bit[1,0] are dev index */ -static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index) +static uint32_t pci_read_config32_index(pci_devfn_t dev, uint32_t index_reg, uint32_t index) { uint32_t dword;
@@ -14,7 +14,7 @@ static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32 return dword; }
-static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +static void pci_write_config32_index(pci_devfn_t dev, uint32_t index_reg, uint32_t index, uint32_t data) { pci_write_config32(dev, index_reg, index);
@@ -22,7 +22,7 @@ static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t } #endif
-static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index) +static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, uint32_t index_reg, uint32_t index) { uint32_t dword;
@@ -38,7 +38,7 @@ static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, u return dword; }
-static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +static void pci_write_config32_index_wait(pci_devfn_t dev, uint32_t index_reg, uint32_t index, uint32_t data) { uint32_t dword;
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index d765fc7..588ae71 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -18,7 +18,7 @@ static inline void print_linkn_in (const char *strval, uint8_t byteval) printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); }
-static uint8_t ht_lookup_capability(device_t dev, uint16_t val) +static uint8_t ht_lookup_capability(pci_devfn_t dev, uint16_t val) { uint8_t pos; uint8_t hdr_type; @@ -51,13 +51,13 @@ static uint8_t ht_lookup_capability(device_t dev, uint16_t val) return pos; }
-static uint8_t ht_lookup_slave_capability(device_t dev) +static uint8_t ht_lookup_slave_capability(pci_devfn_t dev) { return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format }
#if 0 -static uint8_t ht_lookup_host_capability(device_t dev) +static uint8_t ht_lookup_host_capability(pci_devfn_t dev) { return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format } @@ -65,7 +65,7 @@ static uint8_t ht_lookup_host_capability(device_t dev)
static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid) { - device_t dev; + pci_devfn_t dev;
//actually, only for one HT device HT chain, and unitid is 0 #if !CONFIG_HT_CHAIN_UNITID_BASE @@ -111,7 +111,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid } }
-static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) +static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos) { /* Handle bugs in valid hypertransport frequency reporting */ uint16_t freq_cap; @@ -157,7 +157,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) return freq_cap; }
-static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) +static uint8_t ht_read_width_cap(pci_devfn_t dev, uint8_t pos) { uint8_t width_cap = pci_read_config8(dev, pos);
@@ -203,8 +203,8 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) PCI_HT_CAP_SLAVE_FREQ_CAP1)
static int ht_optimize_link( - device_t dev1, uint8_t pos1, unsigned offs1, - device_t dev2, uint8_t pos2, unsigned offs2) + pci_devfn_t dev1, uint8_t pos1, unsigned offs1, + pci_devfn_t dev2, uint8_t pos2, unsigned offs2) { static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; @@ -290,9 +290,9 @@ static int ht_optimize_link( }
#if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo) +static void ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo) #else -static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) +static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) #endif { //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link @@ -348,7 +348,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of } } while((ctrl & (1 << 5)) == 0);
- device_t dev = PCI_DEV(bus, 0, 0); + pci_devfn_t dev = PCI_DEV(bus, 0, 0); last_unitid = next_unitid;
id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -470,9 +470,9 @@ end_of_chain: ;
#if 0 #if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo) +static void ht_setup_chain(pci_devfn_t udev, unsigned upos, struct sys_info *sysinfo) #else -static int ht_setup_chain(device_t udev, unsigned upos) +static int ht_setup_chain(pci_devfn_t udev, unsigned upos) #endif { unsigned offset_unitid = 0; @@ -570,7 +570,7 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, uint32_t dword; uint8_t link_type; unsigned regpos; - device_t dev; + pci_devfn_t dev;
/* This works on an Athlon64 because unimplemented links return 0 */ regpos = 0x98 + (linkn * 0x20); @@ -636,7 +636,7 @@ static int ht_setup_chains(uint8_t ht_c_num) * links needs to be programed to point at bus 0. */ uint8_t upos; - device_t udev; + pci_devfn_t udev; uint8_t i;
#if !CONFIG_RAMINIT_SYSINFO @@ -742,7 +742,7 @@ static int ht_setup_chains_x(void) }
for(nodeid=0; nodeid<nodes; nodeid++) { - device_t dev; + pci_devfn_t dev; uint8_t linkn; dev = PCI_DEV(0, 0x18+nodeid,0); for(linkn = 0; linkn<3; linkn++) { @@ -782,7 +782,7 @@ static int ht_setup_chains_x(void)
for(nodeid = 1; nodeid<nodes; nodeid++) { int i; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,1); for(i = 0; i< 4; i++) { unsigned regpos; diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index 0e0f9f4..fa53068 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -240,10 +240,10 @@ //struct definitions
struct link_pair_st { - device_t udev; + pci_devfn_t udev; uint32_t upos; uint32_t uoffs; - device_t dev; + pci_devfn_t dev; uint32_t pos; uint32_t offs;
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 4213cfb..7072671 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -24,7 +24,7 @@ void setup_resource_map(const unsigned int *register_values, int max) int i; // printk(BIOS_DEBUG, "setting up resource map...."); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = register_values[i] & ~0xfff; @@ -527,7 +527,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) printk(BIOS_SPEW, "setting up CPU%02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; @@ -819,7 +819,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, unsigned base; unsigned index; unsigned limit_reg, base_reg; - device_t device; + pci_devfn_t device;
node_id = ctrl->node_id; index = (node_id << 3); @@ -2233,7 +2233,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, { int ii; uint32_t carry_over; - device_t dev; + pci_devfn_t dev; uint32_t base, limit; uint32_t basek; uint32_t hoist; diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 9da8417..610d7d3 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -6,7 +6,7 @@ #define DIMM_SOCKETS 4 struct mem_controller { unsigned node_id; - device_t f0, f1, f2, f3; + pci_devfn_t f0, f1, f2, f3; uint16_t channel0[DIMM_SOCKETS]; uint16_t channel1[DIMM_SOCKETS]; }; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 92d7f13..3958918 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -78,7 +78,7 @@ void setup_resource_map(const unsigned int *register_values, int max) { int i; for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = register_values[i] & ~0xff; @@ -694,7 +694,7 @@ index: printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; @@ -1017,7 +1017,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, unsigned base; unsigned index; unsigned limit_reg, base_reg; - device_t device; + pci_devfn_t device;
node_id = ctrl->node_id; index = (node_id << 3); @@ -2907,7 +2907,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, { int ii; uint32_t carry_over; - device_t dev; + pci_devfn_t dev; uint32_t base, limit; uint32_t basek; uint32_t hoist; diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index 230459a..aea34f7 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -9,7 +9,7 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns printk(BIOS_DEBUG, "setting up resource map offset....\n"); #endif for(i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg = 0; #if RES_DEBUG @@ -58,7 +58,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int switch (register_values[i]) { case RES_PCI_IO: //PCI { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg = 0; dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h index 25075bd..be2df72 100644 --- a/src/northbridge/amd/lx/northbridge.h +++ b/src/northbridge/amd/lx/northbridge.h @@ -23,7 +23,7 @@ #include <cpu/amd/lxdef.h>
/* northbridge.c */ -unsigned int lx_scan_root_bus(device_t root, unsigned int max); +unsigned int lx_scan_root_bus(pci_devfn_t root, unsigned int max); int sizeram(void);
/* northbridgeinit.c */ diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index 32a1428..60a7585 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -11,7 +11,7 @@ static void print_debug_pci_dev(unsigned dev)
static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -44,7 +44,7 @@ static void dump_pci_device(unsigned dev)
static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -61,7 +61,7 @@ static inline void dump_pci_devices(void)
static inline void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h index 05c3889..a560687 100644 --- a/src/northbridge/intel/e7501/raminit.h +++ b/src/northbridge/intel/e7501/raminit.h @@ -6,7 +6,7 @@ #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
struct mem_controller { - device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller + pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
// SMBus addresses of DIMM slots for each channel, // in order from closest to MCH to furthest away diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index cdf6e7e..543d2ae 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -21,7 +21,7 @@ void print_debug_pci_dev(unsigned dev)
void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -54,7 +54,7 @@ void dump_pci_device(unsigned dev)
void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -71,7 +71,7 @@ void dump_pci_devices(void)
void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 8eb4990..d5fd7ba 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -6,7 +6,7 @@ #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
struct mem_controller { - device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller + pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
// SMBus addresses of DIMM slots for each channel, // in order from closest to MCH to furthest away diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 224dfce..a7c8fcf 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -23,7 +23,7 @@
void gm45_early_init(void) { - const device_t d0f0 = PCI_DEV(0, 0, 0); + const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index b7847c0..84a4ff7 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -35,9 +35,9 @@ /* The PEG settings have to be set before ASPM is setup on DMI. */ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) { - const device_t mch_dev = PCI_DEV(0, 0, 0); - const device_t peg_dev = PCI_DEV(0, 1, 0); - const device_t igd_dev = PCI_DEV(0, 2, 0); + const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); + const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0); + const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0);
u16 reg16; u32 reg32; @@ -115,7 +115,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
static void disable_igd(const sysinfo_t *const sysinfo) { - const device_t mch_dev = PCI_DEV(0, 0, 0); + const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
printk(BIOS_DEBUG, "Disabling IGD.\n");
@@ -136,7 +136,7 @@ static void disable_igd(const sysinfo_t *const sysinfo)
void init_igd(const sysinfo_t *const sysinfo) { - const device_t mch_dev = PCI_DEV(0, 0, 0); + const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
const u8 capid = pci_read_config8(mch_dev, D0F0_CAPID0 + 4); if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) @@ -147,7 +147,7 @@ void init_igd(const sysinfo_t *const sysinfo)
void igd_compute_ggc(sysinfo_t *const sysinfo) { - const device_t mch_dev = PCI_DEV(0, 0, 0); + const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4); if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index e40954a..b399923 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -51,7 +51,7 @@ void init_iommu() /* clear GTT */ u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); if (gtt & 0x400) { /* VT mode */ - device_t igd = PCI_DEV(0, 2, 0); + pci_devfn_t igd = PCI_DEV(0, 2, 0);
/* setup somewhere */ u8 cmd = pci_read_config8(igd, PCI_COMMAND); @@ -70,7 +70,7 @@ void init_iommu()
if (stepping == STEPPING_B3) { MCHBAR8(0xffc) |= 1 << 4; - device_t peg = PCI_DEV(0, 1, 0); + pci_devfn_t peg = PCI_DEV(0, 1, 0); /* FIXME: proper test? */ if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) { int val = pci_read_config32(peg, 0xfc) | (1 << 15); diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index ae34a11..0976f2a 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -117,8 +117,8 @@ static void init_pcie(const int peg_enabled, u8 tmp8; u16 tmp16; u32 tmp; - const device_t mch = PCI_DEV(0, 0, 0); - const device_t pciex = PCI_DEV(0, 1, 0); + const pci_devfn_t mch = PCI_DEV(0, 0, 0); + const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1, peg_enabled?"enabled":"disabled", @@ -167,7 +167,7 @@ static void init_pcie(const int peg_enabled, static void setup_aspm(const stepping_t stepping, const int peg_enabled) { u32 tmp32; - const device_t pciex = PCI_DEV(0, 1, 0); + const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
/* Prerequisites for ASPM: */ if (peg_enabled) { @@ -332,7 +332,7 @@ static void setup_rcrb(const int peg_enabled)
void gm45_late_init(const stepping_t stepping) { - const device_t mch = PCI_DEV(0, 0, 0); + const pci_devfn_t mch = PCI_DEV(0, 0, 0); const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1; const int sdvo_enabled = (MCHBAR16(0x40) >> 8) & 1; const int peg_x16 = (peg_enabled && !sdvo_enabled); diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 34d1eef..7508503 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -68,7 +68,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg; dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0; diff --git a/src/northbridge/intel/i3100/raminit.h b/src/northbridge/intel/i3100/raminit.h index ea6c60f..c046e00 100644 --- a/src/northbridge/intel/i3100/raminit.h +++ b/src/northbridge/intel/i3100/raminit.h @@ -25,7 +25,7 @@ #define DIMM_SOCKETS 4 struct mem_controller { u32 node_id; - device_t f0, f1, f2, f3; + pci_devfn_t f0, f1, f2, f3; u16 channel0[DIMM_SOCKETS]; u16 channel1[DIMM_SOCKETS]; }; diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 77d4463..85d1152 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -40,7 +40,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) int i;
for (i = 0; i < ARRAY_SIZE(register_values); i += 3) { - device_t dev; + pci_devfn_t dev; u32 where; u32 reg; dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0; diff --git a/src/northbridge/intel/i3100/raminit_ep80579.h b/src/northbridge/intel/i3100/raminit_ep80579.h index e84736d..1cd4a9c 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.h +++ b/src/northbridge/intel/i3100/raminit_ep80579.h @@ -23,7 +23,7 @@ #define DIMM_SOCKETS 2 struct mem_controller { u32 node_id; - device_t f0; + pci_devfn_t f0; u16 channel0[DIMM_SOCKETS]; };
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 5394002..ce0c8cd 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -91,7 +91,7 @@ static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup, static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out) { u16 status; - device_t dev = d->branch->branchdev; + pci_devfn_t dev = d->branch->branchdev;
int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; @@ -117,7 +117,7 @@ static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
static void i5000_clear_fbd_errors(void) { - device_t dev16_1, dev16_2; + pci_devfn_t dev16_1, dev16_2;
dev16_1 = PCI_ADDR(0, 16, 1, 0); dev16_2 = PCI_ADDR(0, 16, 2, 0); @@ -146,7 +146,7 @@ static void i5000_clear_fbd_errors(void)
static int i5000_branch_reset(struct i5000_fbd_branch *b) { - device_t dev = b->branchdev; + pci_devfn_t dev = b->branchdev;
pci_write_config8(dev, I5000_FBDRST, 0x00);
@@ -342,7 +342,7 @@ static int i5000_read_spd_data(struct i5000_fbdimm *d) static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) { u16 status; - device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + pci_devfn_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; int timeout = 1000; @@ -365,7 +365,7 @@ static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out) { u16 status; - device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + pci_devfn_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; int timeout = 1000; @@ -663,7 +663,7 @@ static int i5000_amb_preinit(struct i5000_fbdimm *d) static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state) { int timeout = 10000; - device_t dev = b->branchdev; + pci_devfn_t dev = b->branchdev;
printk(BIOS_DEBUG, " FBD state branch %d: %02x,", b->num, state);
@@ -686,7 +686,7 @@ static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state) static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c) { int i = 10; - device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + pci_devfn_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
printk(BIOS_DEBUG, " waiting for pattern recognition..."); @@ -708,7 +708,7 @@ static const char *pattern_names[16] = {
static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait) { - device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + pci_devfn_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n", @@ -725,7 +725,7 @@ static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wai static int i5000_set_ambpresent(struct i5000_fbd_channel *c) { int i; - device_t branchdev = c->branch->branchdev; + pci_devfn_t branchdev = c->branch->branchdev; u16 ambpresent = 0x8000;
for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { @@ -745,7 +745,7 @@ static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad) { - device_t branchdev = c->branch->branchdev; + pci_devfn_t branchdev = c->branch->branchdev; int off = c->num ? 0x100 : 0; u32 portctl; int i, cnt = 1000; @@ -838,7 +838,7 @@ static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
static int i5000_setup_channel(struct i5000_fbd_channel *c) { - device_t branchdev = c->branch->branchdev; + pci_devfn_t branchdev = c->branch->branchdev; int off = c->branch->num ? 0x100 : 0; u32 val;
@@ -862,7 +862,7 @@ static int i5000_setup_channel(struct i5000_fbd_channel *c)
static int i5000_link_training0(struct i5000_fbd_branch *b) { - device_t branchdev = b->branchdev; + pci_devfn_t branchdev = b->branchdev;
pci_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
@@ -1191,7 +1191,7 @@ static int get_dmir(u8 *rankmap, int *_set, int limit) static int i5000_setup_dmir(struct i5000_fbd_branch *b) { struct i5000_fbdimm *d; - device_t dev = b->branchdev; + pci_devfn_t dev = b->branchdev; u8 rankmap = 0, dmir = 0; u32 dmirval = 0; int i, set, rankoffset = 0, ranksize = 0, ranks = 0; @@ -1255,7 +1255,7 @@ static int i5000_setup_dmir(struct i5000_fbd_branch *b)
static void i5000_setup_interleave(struct i5000_fbd_setup *setup) { - device_t dev16 = PCI_ADDR(0, 16, 1, 0); + pci_devfn_t dev16 = PCI_ADDR(0, 16, 1, 0); u32 mir0, mir1, mir2, size0, size1, minsize, tmp;
size0 = i5000_setup_dmir(&setup->branch[1]) >> 12; @@ -1294,7 +1294,7 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup)
static int i5000_dram_timing_init(struct i5000_fbd_setup *setup) { - device_t dev16 = PCI_ADDR(0, 16, 1, 0); + pci_devfn_t dev16 = PCI_ADDR(0, 16, 1, 0); u32 tolm, drta, drtb, mc, mca; int t_wrc, bl2;
@@ -1458,7 +1458,7 @@ static void i5000_reserved_register_init(struct i5000_fbd_setup *setup) } static void i5000_dump_error_registers(void) { - device_t dev = PCI_ADDR(0, 16, 1, 0); + pci_devfn_t dev = PCI_ADDR(0, 16, 1, 0);
printk(BIOS_ERR, "Dump of FBD error registers:\n" "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n" @@ -1541,7 +1541,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup) { int fbd, fsb, ddrfrq, ddrfrqnow; msr_t msr; - device_t dev = PCI_ADDR(0, 16, 1, 0); + pci_devfn_t dev = PCI_ADDR(0, 16, 1, 0);
switch(setup->ddr_speed) { case DDR_667MHZ: diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h index 021e6fa..e8e20e1 100644 --- a/src/northbridge/intel/i5000/raminit.h +++ b/src/northbridge/intel/i5000/raminit.h @@ -281,7 +281,7 @@ struct i5000_fbd_channel { struct i5000_fbd_branch { struct i5000_fbd_channel channel[I5000_MAX_CHANNEL]; struct i5000_fbd_setup *setup; - device_t branchdev; + pci_devfn_t branchdev; int num; int used; /* memory size in MB on this branch */ diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c index ed26fad..1e481f1 100644 --- a/src/northbridge/intel/i855/debug.c +++ b/src/northbridge/intel/i855/debug.c @@ -28,7 +28,7 @@ static void print_debug_pci_dev(unsigned dev)
static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -63,7 +63,7 @@ static void dump_pci_device(unsigned dev)
static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 397bd4b..7c3558d 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -28,7 +28,7 @@
void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -66,7 +66,7 @@ void dump_pci_device(unsigned dev)
void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 4a208ce..73554a4 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -135,7 +135,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion) /* Initialize IGD OpRegion, called from ACPI code */ int init_igd_opregion(igd_opregion_t * opregion) { - device_t igd; + pci_devfn_t igd; u16 reg16;
memset((void *)opregion, 0, sizeof(igd_opregion_t)); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 3917288..1245b32 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -50,7 +50,7 @@ typedef unsigned char u8; typedef unsigned short u16; typedef unsigned int u32; -typedef u32 device_t; +typedef u32 pci_devfn_t; #endif
#include "nehalem.h" diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index 289b315..fcb748b 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -38,7 +38,7 @@ #define DUMPNORTH() #endif
-static void do_ram_command(device_t dev, u8 command) +static void do_ram_command(pci_devfn_t dev, u8 command) { u8 reg;
@@ -62,7 +62,7 @@ static void do_ram_command(device_t dev, u8 command) * * @param dev The northbridge's CPU Host Interface (D0F2). */ -static void c7_cpu_setup(device_t dev) +static void c7_cpu_setup(pci_devfn_t dev) { /* Host bus interface registers (D0F2 0x50-0x67) */ /* Request phase control */ @@ -380,7 +380,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
static void sdram_set_post(const struct mem_controller *ctrl) { - device_t dev = ctrl->d0f3; + pci_devfn_t dev = ctrl->d0f3;
/* Enable multipage mode. */ pci_write_config8(dev, 0x69, 0x03); @@ -393,7 +393,7 @@ static void sdram_set_post(const struct mem_controller *ctrl) pci_write_config16(dev, 0xa4, 0x0010); }
-static void sdram_enable(device_t dev, u8 *rank_address) +static void sdram_enable(pci_devfn_t dev, u8 *rank_address) { u8 i;
diff --git a/src/northbridge/via/cn700/raminit.h b/src/northbridge/via/cn700/raminit.h index 89ea0d6..173a7b9 100644 --- a/src/northbridge/via/cn700/raminit.h +++ b/src/northbridge/via/cn700/raminit.h @@ -24,7 +24,7 @@ #define DIMM_SOCKETS 1 /* Only one works, for now. */
struct mem_controller { - device_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0; + pci_devfn_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0; u8 channel0[DIMM_SOCKETS]; };
diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c index 39e1753..2475be3 100644 --- a/src/northbridge/via/cx700/early_smbus.c +++ b/src/northbridge/via/cx700/early_smbus.c @@ -196,7 +196,7 @@ static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int
static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* The CX700 ISA Bridge (0x1106, 0x8324) is hardcoded to this location, * no need to probe. diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index fabd7ff..fd1e7ad 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -1235,7 +1235,7 @@ static void sdram_enable(const struct mem_controller *ctrl) { u8 reg8; u8 val, i; - device_t dev; + pci_devfn_t dev; u8 dl, dh; u32 quot;
diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c index da2a559..69ac46b 100644 --- a/src/northbridge/via/vx800/early_smbus.c +++ b/src/northbridge/via/vx800/early_smbus.c @@ -133,7 +133,7 @@ static unsigned int get_spd_data(unsigned int dimm, unsigned int offset)
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0);
diff --git a/src/northbridge/via/vx800/pci_rawops.h b/src/northbridge/via/vx800/pci_rawops.h index 33eebc4..2993b0e 100644 --- a/src/northbridge/via/vx800/pci_rawops.h +++ b/src/northbridge/via/vx800/pci_rawops.h @@ -35,7 +35,7 @@ struct VIA_PCI_REG_INIT_TABLE { u8 Value; };
-static void pci_modify_config8(device_t dev, unsigned where, u8 orval, u8 mask) +static void pci_modify_config8(pci_devfn_t dev, unsigned where, u8 orval, u8 mask) { u8 data = pci_read_config8(dev, where); data &= (~mask); @@ -47,7 +47,7 @@ static void via_pci_inittable(u8 chipversion, const struct VIA_PCI_REG_INIT_TABLE *initdata) { u8 i = 0; - device_t devbxdxfx; + pci_devfn_t devbxdxfx; for (i = 0;; i++) { if ((initdata[i].Mask == 0) && (initdata[i].Value == 0) && (initdata[i].Bus == 0) diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index 487dab4..3117701 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -69,7 +69,7 @@ void SetUMARam(void) { #if 1 u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t vga_dev = PCI_DEV(0, 1, 0), d0f0_dev = PCI_DEV(0, 0, 0); + pci_devfn_t vga_dev = PCI_DEV(0, 1, 0), d0f0_dev = PCI_DEV(0, 0, 0); u8 ByteVal, temp; const UMARAM *pUMARamTable; u16 UmaSize; diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c index 14dd9ec..67d10d1 100644 --- a/src/northbridge/via/vx900/early_smbus.c +++ b/src/northbridge/via/vx900/early_smbus.c @@ -79,7 +79,7 @@ u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; u8 reg8; u32 smbus_dev = (u32) SMBUS_IO_BASE;
diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index d00daa3..ccf9415 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -44,12 +44,12 @@ uint64_t get_uma_memory_base(void);
/* We use these throughout the code. They really belong in a generic part of * coreboot, but until bureaucracy gets them there, we still need them */ -void dump_pci_device(device_t dev); -void pci_mod_config8(device_t dev, unsigned int where, +void dump_pci_device(pci_devfn_t dev); +void pci_mod_config8(pci_devfn_t dev, unsigned int where, uint8_t clr_mask, uint8_t set_mask); -void pci_mod_config16(device_t dev, unsigned int where, +void pci_mod_config16(pci_devfn_t dev, unsigned int where, uint16_t clr_mask, uint16_t set_mask); -void pci_mod_config32(device_t dev, unsigned int where, +void pci_mod_config32(pci_devfn_t dev, unsigned int where, uint32_t clr_mask, uint32_t set_mask);
#endif /* __VX900_H */ diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h index e877f2a..265a5af 100644 --- a/src/southbridge/amd/amd8111/amd8111.h +++ b/src/southbridge/amd/amd8111/amd8111.h @@ -1,12 +1,14 @@ #ifndef AMD8111_H #define AMD8111_H
-#include "chip.h" +#ifdef __PRE_RAM__ +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); + +#else /* !__PRE_RAM__ */
+#include "chip.h" void amd8111_enable(device_t dev);
-#ifdef __PRE_RAM__ -void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -#endif +#endif /* __PRE_RAM__ */
#endif /* AMD8111_H */ diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index ece99ed..83af1d0 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -4,7 +4,7 @@ /* by yhlu 2005.10 */ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. * There can only be one 8111 on a hypertransport chain/bus. @@ -19,7 +19,7 @@ static unsigned get_sbdn(unsigned bus)
static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; + pci_devfn_t dev; uint8_t byte;
dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI @@ -48,7 +48,7 @@ void hard_reset(void)
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - device_t dev; + pci_devfn_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
@@ -61,7 +61,7 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
static void soft_reset_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; + pci_devfn_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index aed4ebb..4c0ace5 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -4,7 +4,7 @@
static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; uint8_t enable;
dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..b606352 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev;
printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -69,7 +69,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8;
//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8;
//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 34375c5..444d632 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -32,7 +32,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev;
printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/rs690/early_setup.c b/src/southbridge/amd/rs690/early_setup.c index b4377f4..e5e19fc 100644 --- a/src/southbridge/amd/rs690/early_setup.c +++ b/src/southbridge/amd/rs690/early_setup.c @@ -23,49 +23,49 @@ #define NBMISC_INDEX 0x60 #define NBMC_INDEX 0xE8
-static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) +static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) { pci_write_config32(dev, index_reg, index); return pci_read_config32(dev, index_reg + 0x4); }
-static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) +static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) { pci_write_config32(dev, index_reg, index /* | 0x80 */ ); pci_write_config32(dev, index_reg + 0x4, data); }
-static u32 nbmisc_read_index(device_t nb_dev, u32 index) +static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMISC_INDEX, (index)); }
-static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) +static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); }
-static u32 htiu_read_index(device_t nb_dev, u32 index) +static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); }
-static void htiu_write_index(device_t nb_dev, u32 index, u32 data) +static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); }
-static u32 nbmc_read_index(device_t nb_dev, u32 index) +static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMC_INDEX, (index)); }
-static void nbmc_write_index(device_t nb_dev, u32 index, u32 data) +static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); }
-static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -77,7 +77,7 @@ static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } }
-static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -89,7 +89,7 @@ static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } }
-static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -101,7 +101,7 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } }
-static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, +static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask, u8 val) { u8 reg_old, reg; @@ -113,7 +113,7 @@ static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, } }
-static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -152,7 +152,7 @@ static void get_cpu_rev(void) printk(BIOS_INFO, "CPU Rev is K8_10.\n"); }
-static u8 get_nb_rev(device_t nb_dev) +static u8 get_nb_rev(pci_devfn_t nb_dev) { u32 reg; reg = pci_read_config32(nb_dev, 0x00); @@ -176,7 +176,7 @@ static void rs690_htinit(void) /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0, rs690_f0; + pci_devfn_t k8_f0, rs690_f0; u32 reg; u8 reg8; u8 k8_ht_freq; @@ -231,7 +231,7 @@ static void rs690_htinit(void) *******************************************************/ static void k8_optimization(void) { - device_t k8_f0, k8_f2, k8_f3; + pci_devfn_t k8_f0, k8_f2, k8_f3; msr_t msr;
printk(BIOS_INFO, "k8_optimization()\n"); @@ -270,7 +270,7 @@ static void k8_optimization(void) /***************************************** * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE *****************************************/ -static void rs690_por_pcicfg_init(device_t nb_dev) +static void rs690_por_pcicfg_init(pci_devfn_t nb_dev) { /* enable PCI Memory Access */ set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02); @@ -322,7 +322,7 @@ static void rs690_por_pcicfg_init(device_t nb_dev) /***************************************** * Compliant with CIM_33's ATINB_MCIndex_POR_TABLE *****************************************/ -static void rs690_por_mc_index_init(device_t nb_dev) +static void rs690_por_mc_index_init(pci_devfn_t nb_dev) { set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F); set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060); @@ -337,7 +337,7 @@ static void rs690_por_mc_index_init(device_t nb_dev) * Compliant with CIM_33's ATINB_MISCIND_POR_TABLE * Compliant with CIM_33's MISC_INIT_TBL *****************************************/ -static void rs690_por_misc_index_init(device_t nb_dev) +static void rs690_por_misc_index_init(pci_devfn_t nb_dev) { /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL * Block non-snoop DMA request if PMArbDis is set. @@ -390,7 +390,7 @@ static void rs690_por_misc_index_init(device_t nb_dev) /***************************************** * Compliant with CIM_33's ATINB_HTIUNBIND_POR_TABLE *****************************************/ -static void rs690_por_htiu_index_init(device_t nb_dev) +static void rs690_por_htiu_index_init(pci_devfn_t nb_dev) { /* 0xBC: * Enables GSM mode for C1e or C3 with pop-up @@ -423,7 +423,7 @@ static void rs690_por_htiu_index_init(device_t nb_dev) * POR: Power On Reset * RPR: Register Programming Requirements *****************************************/ -static void rs690_por_init(device_t nb_dev) +static void rs690_por_init(pci_devfn_t nb_dev) { printk(BIOS_INFO, "rs690_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */ @@ -462,7 +462,7 @@ static void rs690_before_pci_init(void) */ static void rs690_early_setup(void) { - device_t nb_dev = PCI_DEV(0, 0, 0); + pci_devfn_t nb_dev = PCI_DEV(0, 0, 0); printk(BIOS_INFO, "rs690_early_setup()\n");
/*ATINB_PrepareInit */ diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index d35ecdd..f9719eb 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -23,49 +23,49 @@ #define NBMISC_INDEX 0x60 #define NBMC_INDEX 0xE8
-static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) +static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) { pci_write_config32(dev, index_reg, index); return pci_read_config32(dev, index_reg + 0x4); }
-static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) +static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) { pci_write_config32(dev, index_reg, index /* | 0x80 */ ); pci_write_config32(dev, index_reg + 0x4, data); }
-static u32 nbmisc_read_index(device_t nb_dev, u32 index) +static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMISC_INDEX, (index)); }
-static void nbmisc_write_index(device_t nb_dev, u32 index, u32 data) +static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); }
-static u32 htiu_read_index(device_t nb_dev, u32 index) +static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); }
-static void htiu_write_index(device_t nb_dev, u32 index, u32 data) +static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); }
-static u32 nbmc_read_index(device_t nb_dev, u32 index) +static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) { return nb_read_index((nb_dev), NBMC_INDEX, (index)); }
-static void nbmc_write_index(device_t nb_dev, u32 index, u32 data) +static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) { nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); }
-static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -77,7 +77,7 @@ static void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } }
-static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -89,7 +89,7 @@ static void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } }
-static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -102,7 +102,7 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, } /* family 10 only, for reg > 0xFF */ #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 -static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, +static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -118,7 +118,7 @@ static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 m #endif
-static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, +static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask, u8 val) { u8 reg_old, reg; @@ -130,7 +130,7 @@ static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, } }
-static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, +static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -159,7 +159,7 @@ static u8 cpu_core_number(void) } #endif
-static u8 get_nb_rev(device_t nb_dev) +static u8 get_nb_rev(pci_devfn_t nb_dev) { u8 reg; reg = pci_read_config8(nb_dev, 0x89); /* copy from CIM, can't find in doc */ @@ -207,7 +207,7 @@ static void rs780_htinit(void) /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t cpu_f0, rs780_f0, clk_f1; + pci_devfn_t cpu_f0, rs780_f0, clk_f1; u32 reg; u8 cpu_ht_freq, ibias;
@@ -303,7 +303,7 @@ static void rs780_htinit(void) *******************************************************/ static void k8_optimization(void) { - device_t k8_f0, k8_f2, k8_f3; + pci_devfn_t k8_f0, k8_f2, k8_f3; msr_t msr;
printk(BIOS_INFO, "k8_optimization()\n"); @@ -345,7 +345,7 @@ static void k8_optimization(void) #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 static void fam10_optimization(void) { - device_t cpu_f0, cpu_f2, cpu_f3; + pci_devfn_t cpu_f0, cpu_f2, cpu_f3; u32 val;
printk(BIOS_INFO, "fam10_optimization()\n"); @@ -410,7 +410,7 @@ static void fam10_optimization(void) /***************************************** * rs780_por_pcicfg_init() *****************************************/ -static void rs780_por_pcicfg_init(device_t nb_dev) +static void rs780_por_pcicfg_init(pci_devfn_t nb_dev) { /* enable PCI Memory Access */ set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02); @@ -460,7 +460,7 @@ static void rs780_por_pcicfg_init(device_t nb_dev) set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x02); }
-static void rs780_por_mc_index_init(device_t nb_dev) +static void rs780_por_mc_index_init(pci_devfn_t nb_dev) { set_nbmc_enable_bits(nb_dev, 0x7A, ~0xFFFFFF80, 0x0000005F); set_nbmc_enable_bits(nb_dev, 0xD8, ~0x00000000, 0x00600060); @@ -471,7 +471,7 @@ static void rs780_por_mc_index_init(device_t nb_dev) set_nbmc_enable_bits(nb_dev, 0xE9, ~0x00000000, 0x003E003E); }
-static void rs780_por_misc_index_init(device_t nb_dev) +static void rs780_por_misc_index_init(pci_devfn_t nb_dev) { /* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL * Block non-snoop DMA request if PMArbDis is set. @@ -528,7 +528,7 @@ static void rs780_por_misc_index_init(device_t nb_dev) /***************************************** * Some setting is from rpr. Some is from CIMx. *****************************************/ -static void rs780_por_htiu_index_init(device_t nb_dev) +static void rs780_por_htiu_index_init(pci_devfn_t nb_dev) { #if 0 /* get from rpr. */ set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17); @@ -587,7 +587,7 @@ static void rs780_por_htiu_index_init(device_t nb_dev) * POR: Power On Reset * RPR: Register Programming Requirements *****************************************/ -static void rs780_por_init(device_t nb_dev) +static void rs780_por_init(pci_devfn_t nb_dev) { printk(BIOS_INFO, "rs780_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */ @@ -625,7 +625,7 @@ static void rs780_before_pci_init(void)
static void rs780_early_setup(void) { - device_t nb_dev = PCI_DEV(0, 0, 0); + pci_devfn_t nb_dev = PCI_DEV(0, 0, 0); printk(BIOS_INFO, "rs780_early_setup()\n");
/* The printk(BIOS_INFO, s) below cause the system unstable. */ diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index c49420b..44909f5 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg) /* RPR 2.1: Get SB ASIC Revision. */ static u8 get_sb600_revision(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) { @@ -67,7 +67,7 @@ static void sb600_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -196,7 +196,7 @@ void soft_reset(void) void sb600_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev;
/* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -241,7 +241,7 @@ void sb600_pci_port80(void) void sb600_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32;
/* Enable LPC controller */ @@ -260,7 +260,7 @@ void sb600_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb600_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte;
printk(BIOS_INFO, "sb600_devices_por_init()\n"); @@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void) */ static void sb600_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte;
/* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h index 88cff44..13d703f 100644 --- a/src/southbridge/amd/sb600/sb600.h +++ b/src/southbridge/amd/sb600/sb600.h @@ -21,6 +21,7 @@ #define SB600_H
#include <device/pci_ids.h> +#include <rules.h> #include "chip.h"
/* Power management index/data registers */ @@ -33,9 +34,12 @@ extern void pm_iowrite(u8 reg, u8 value); extern u8 pm_ioread(u8 reg); extern void pm2_iowrite(u8 reg, u8 value); extern u8 pm2_ioread(u8 reg); + +#if ENV_RAMSTAGE extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
void sb600_enable(device_t dev); +#endif /* ENV_RAMSTAGE */
void sb600_lpc_port80(void); void sb600_pci_port80(void); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 50909f8..3149dfe 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -79,7 +79,7 @@ static void sb700_acpi_init(void) /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id, enable_14Mhz, byte; u8 rev = 0;
@@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void) { u8 reg8; u32 reg32; - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ /* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!! @@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8;
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8;
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -290,7 +290,7 @@ void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) void sb7xx_51xx_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev;
/* P2P Bridge */ dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void) void sb7xx_51xx_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; u32 reg32;
/* Enable LPC controller */ @@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb700_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte; #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; @@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void) */ static void sb700_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte;
/* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index c4b91e0..f39c068 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -21,6 +21,7 @@ #define SB700_H
#include <device/pci_ids.h> +#include <rules.h> #include "chip.h"
/* Power management index/data registers */ @@ -44,7 +45,6 @@ extern void pm_iowrite(u8 reg, u8 value); extern u8 pm_ioread(u8 reg); extern void pm2_iowrite(u8 reg, u8 value); extern u8 pm2_ioread(u8 reg); -extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
#define REV_SB700_A11 0x11 #define REV_SB700_A12 0x12 @@ -58,7 +58,10 @@ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); * The differentiate is 0x28, isn't it? */ #define get_sb700_revision(sm_dev) (pci_read_config8((sm_dev), 0x08) - 0x28)
+#if ENV_RAMSTAGE void sb7xx_51xx_enable(device_t dev); +extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); +#endif /* ENV_RAMSTAGE */
#ifdef __PRE_RAM__ void sb7xx_51xx_lpc_port80(void); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index f9eed11..399ad42 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -77,7 +77,7 @@ static void sb800_acpi_init(void) /* RPR 2.28 Get SB ASIC Revision.*/ static u8 get_sb800_revision(void) { - device_t dev; + pci_devfn_t dev; u8 rev_id; u8 rev = 0;
@@ -127,7 +127,7 @@ void sb800_clk_output_48Mhz(void) static void sb800_lpc_init(void) { u8 reg8; - device_t dev; + pci_devfn_t dev;
//dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */ dev = PCI_DEV(0, 0x14, 0); @@ -170,7 +170,7 @@ static void sb800_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. */ dev = PCI_DEV(bus, 0x14, 0);//pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); @@ -242,7 +242,7 @@ void soft_reset(void) void sb800_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev;
/* P2P Bridge */ dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0); @@ -348,7 +348,7 @@ struct pm_entry const pm_table[] = void sb800_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev;
/* Enable LPC controller */ byte = pmio_read(0xEC); @@ -365,7 +365,7 @@ void sb800_lpc_port80(void) /* sbDevicesPorInitTable */ static void sb800_devices_por_init(void) { - device_t dev; + pci_devfn_t dev; u8 byte;
printk(BIOS_INFO, "sb800_devices_por_init()\n"); @@ -547,7 +547,7 @@ static void sb800_pmio_por_init(void) */ static void sb800_pci_cfg(void) { - device_t dev; + pci_devfn_t dev; u8 byte;
/* SMBus Device, BDF:0-20-0 */ diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h index 5d299c8..5aa693a 100644 --- a/src/southbridge/amd/sb800/sb800.h +++ b/src/southbridge/amd/sb800/sb800.h @@ -21,6 +21,7 @@ #define SB800_H
#include <device/pci_ids.h> +#include <rules.h> #include "chip.h"
/* Power management index/data registers */ @@ -44,13 +45,12 @@ void pm_iowrite(u8 reg, u8 value); u8 pm_ioread(u8 reg); void pm2_iowrite(u8 reg, u8 value); u8 pm2_ioread(u8 reg); -void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
#define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12
-#ifdef __PRE_RAM__ +#if !ENV_RAMSTAGE void sb800_lpc_port80(void); void sb800_pci_port80(void); void sb800_clk_output_48Mhz(void); @@ -58,8 +58,9 @@ void sb800_clk_output_48Mhz(void); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-#else +#else /* ENV_RAMSTAGE */ +void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); void sb800_enable(device_t dev); -#endif +#endif /* !ENV_RAMSTAGE */
#endif /* SB800_H */ diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..fe0fded 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -24,7 +24,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
@@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void)
static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old;
@@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void)
unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -134,7 +134,7 @@ void soft_reset(void)
static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -162,7 +162,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev;
//F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 636da2e..7306578 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -24,7 +24,7 @@
static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 7ba2e88..ba50e3b 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -27,7 +27,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index f2d04dd..e02bbeb 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -42,7 +42,7 @@ static uint16_t read16p (uintptr_t addr) which is done at the end of raminit. */ void early_thermal_init(void) { - device_t dev; + pci_devfn_t dev; msr_t msr;
dev = PCI_DEV(0x0, 0x1f, 0x6); diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index ea2bf38..fd24b41 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -36,8 +36,8 @@ */ void enable_usb_bar(void) { - device_t usb0 = PCH_EHCI1_DEV; - device_t usb1 = PCH_EHCI2_DEV; + pci_devfn_t usb0 = PCH_EHCI1_DEV; + pci_devfn_t usb1 = PCH_EHCI2_DEV; u32 cmd;
/* USB Controller 1 */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 37a0b64..f80f859 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -35,11 +35,12 @@ static int pch_type = -1;
int pch_silicon_revision(void) { - device_t dev;
#ifdef __SMM__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif
@@ -50,11 +51,12 @@ int pch_silicon_revision(void)
int pch_silicon_type(void) { - device_t dev;
#ifdef __SMM__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 029da9f..33b947b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -21,6 +21,8 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
+#include <rules.h> + /* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ #define PCH_TYPE_PPT 0x1e /* IvyBridge */ @@ -61,19 +63,22 @@ void intel_pch_finalize_smm(void); #endif
#if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) -#if !defined(__SMM__) + +#if ENV_RAMSTAGE #include "chip.h" +#include <device/device.h> void pch_enable(device_t dev); -#endif +#endif /* ENV_RAMSTAGE */ + +#if ENV_RAMSTAGE || ENV_SMM int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if CONFIG_ELOG void pch_log_state(void); -#endif -#else /* __PRE_RAM__ */ +#endif /* CONFIG_ELOG */ +#else /* ENV_RAMSTAGE || ENV_SMM */ void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); @@ -92,13 +97,13 @@ struct southbridge_usb_port
#ifndef __ROMCC__ extern const struct southbridge_usb_port mainboard_usb_ports[14]; -#endif +#endif /* __ROMCC__ */
void early_usb_init (const struct southbridge_usb_port *portmap);
-#endif -#endif +#endif /* ENV_RAMSTAGE || ENV_SMM */ +#endif /* !ASSEMBLER */
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f69c1f4..c6c18ff 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -264,7 +264,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c b/src/southbridge/intel/fsp_bd82x6x/early_smbus.c index c5459cb..f9f5823 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_smbus.c @@ -73,7 +73,7 @@ static int smbus_wait_until_done(u16 smbus_base) */ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/fsp_bd82x6x/early_usb.c b/src/southbridge/intel/fsp_bd82x6x/early_usb.c index ba546e0..d66fc99 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_usb.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_usb.c @@ -36,8 +36,8 @@ */ void enable_usb_bar(void) { - device_t usb0 = PCH_EHCI1_DEV; - device_t usb1 = PCH_EHCI2_DEV; + pci_devfn_t usb0 = PCH_EHCI1_DEV; + pci_devfn_t usb1 = PCH_EHCI2_DEV; u32 cmd;
/* USB Controller 1 */ diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index c1e9b71..76e7af1 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -22,6 +22,8 @@ #ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H
+#include <rules.h> + /* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ #define PCH_TYPE_PPT 0x1e /* IvyBridge */ @@ -62,7 +64,7 @@ void intel_pch_finalize_smm(void); #endif
#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) -#if !defined(__PRE_RAM__) && !defined(__SMM__) +#if ENV_RAMSTAGE #include "chip.h" int pch_silicon_revision(void); int pch_silicon_type(void); @@ -71,7 +73,7 @@ void pch_enable(device_t dev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if CONFIG_ELOG void pch_log_state(void); -#endif +#endif /* CONFIG_ELOG */ #else /* writes an address and one byte of data */ s16 smbus_write_single_byte(u8 device, u8 address, u8 data); diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c index c1da54b..e430965 100644 --- a/src/southbridge/intel/fsp_rangeley/early_smbus.c +++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c @@ -27,7 +27,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c index 40759b3..0657877 100644 --- a/src/southbridge/intel/fsp_rangeley/early_usb.c +++ b/src/southbridge/intel/fsp_rangeley/early_usb.c @@ -35,7 +35,7 @@ */ void enable_usb_bar(void) { - device_t usb0 = SOC_EHCI1_DEV; + pci_devfn_t usb0 = SOC_EHCI1_DEV; u32 cmd;
/* USB Controller 0 */ diff --git a/src/southbridge/intel/i3100/early_lpc.c b/src/southbridge/intel/i3100/early_lpc.c index 1133b8d..ca381fe 100644 --- a/src/southbridge/intel/i3100/early_lpc.c +++ b/src/southbridge/intel/i3100/early_lpc.c @@ -20,7 +20,7 @@
static void i3100_enable_superio(void) { - device_t dev = PCI_DEV(0x0, 0x1f, 0x0); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Enable decoding of I/O locations for SuperIO devices */ pci_write_config16(dev, 0x80, 0x0010); @@ -32,7 +32,7 @@ static void i3100_enable_superio(void)
static void i3100_halt_tco_timer(void) { - device_t dev = PCI_DEV(0x0, 0x1f, 0x0); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Temporarily enable the ACPI I/O range at 0x4000 */ pci_write_config32(dev, 0x40, 0x4000 | (1 << 0)); diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c index 484627c..b409035 100644 --- a/src/southbridge/intel/i3100/early_smbus.c +++ b/src/southbridge/intel/i3100/early_smbus.c @@ -24,7 +24,7 @@
static void enable_smbus(void) { - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
printk(BIOS_SPEW, "SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); diff --git a/src/southbridge/intel/i3100/i3100.h b/src/southbridge/intel/i3100/i3100.h index 59c2852..ad0264e 100644 --- a/src/southbridge/intel/i3100/i3100.h +++ b/src/southbridge/intel/i3100/i3100.h @@ -19,6 +19,9 @@
#ifndef SOUTHBRIDGE_INTEL_I3100_I3100_H #define SOUTHBRIDGE_INTEL_I3100_I3100_H + +#include <device/device.h> +#include <rules.h> #include "chip.h"
#define SATA_CMD 0x04 @@ -40,6 +43,8 @@ #define SATA_MODE_IDE 0x00 #define SATA_MODE_AHCI 0x01
+#ifdef ENV_RAMSTAGE void i3100_enable(device_t dev); +#endif /* ENV_RAMSTAGE */
#endif diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index a2f055b..4a3d9d8 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -27,7 +27,7 @@
void enable_pm(void) { - device_t dev; + pci_devfn_t dev; u8 reg8; u16 reg16;
diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 80a4de9..898a96f 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -28,7 +28,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; u8 reg8; u16 reg16;
diff --git a/src/southbridge/intel/i82801ax/early_smbus.c b/src/southbridge/intel/i82801ax/early_smbus.c index 104875a..7c4ed11 100644 --- a/src/southbridge/intel/i82801ax/early_smbus.c +++ b/src/southbridge/intel/i82801ax/early_smbus.c @@ -29,7 +29,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically (D31:F3). */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/i82801bx/early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c index a87a4a7..7c0c750 100644 --- a/src/southbridge/intel/i82801bx/early_smbus.c +++ b/src/southbridge/intel/i82801bx/early_smbus.c @@ -29,7 +29,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically (D31:F3). */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index c61de85..8500ba2 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -26,7 +26,7 @@
void enable_smbus(void) { - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index c7d7e77..2a58372 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -31,14 +31,17 @@ #ifndef I82801DX_H #define I82801DX_H
+#include <rules.h> + #if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) +#if ENV_RAMSTAGE #include "chip.h" +#include <device/device.h> extern void i82801dx_enable(device_t dev); -#else +#else /* !ENV_RAMSTAGE */ void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); -#endif +#endif /* ENV_RAMSTAGE */ #endif
#define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 6375876..f8c6fa0 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -245,7 +245,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/southbridge/intel/i82801dx/tco_timer.c b/src/southbridge/intel/i82801dx/tco_timer.c index a778d08..cb3d736 100644 --- a/src/southbridge/intel/i82801dx/tco_timer.c +++ b/src/southbridge/intel/i82801dx/tco_timer.c @@ -22,7 +22,7 @@ static void i82801dx_halt_tco_timer(void) { /* Set the LPC device statically. */ - device_t dev = PCI_DEV(0x0, 0x1f, 0x0); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x0);
/* Temporarily set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index 979b842..a0364ad 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -4,7 +4,7 @@
static void enable_smbus(void) { - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
printk(BIOS_SPEW, "SMBus controller enabled\n");
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 32eccae..8573105 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -27,7 +27,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 4624841..eea42ce 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -27,6 +27,9 @@ * again. But handling static BARs is a generic problem that should be * solved in the device allocator. */ + +#include <rules.h> + #define SMBUS_IO_BASE 0x0400 /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 @@ -42,15 +45,18 @@ #define DEBUG_PERIODIC_SMIS 0
#if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) + +#if ENV_RAMSTAGE #include "chip.h" +#include <device/device.h> extern void i82801gx_enable(device_t dev); -#else +#else /* !ENV_RAMSTAGE */ + void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); int southbridge_detect_s3_resume(void); -#endif -#endif +#endif /* ENV_RAMSTATE */ +#endif /* !__ASSEMBLER__ */
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index e83c722..8c42ee9 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -245,7 +245,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 1e3b517..dc45092 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -23,7 +23,7 @@
void i82801ix_early_init(void) { - const device_t d31f0 = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
/* Set up RCBA. */ pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 0393c3d..50d2759 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -28,7 +28,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index cf02b9e..7a57d7e 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -27,7 +27,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index e765943..8acfc91 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -27,7 +27,7 @@ which is done at the end of raminit. */ void early_thermal_init(void) { - device_t dev; + pci_devfn_t dev; msr_t msr;
dev = PCI_DEV(0x0, 0x1f, 0x6); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 12e9345..67955eb 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -65,6 +65,7 @@ void intel_pch_finalize_smm(void); #if !defined(__PRE_RAM__) #if !defined(__SMM__) #include "chip.h" +#include <device/device.h> void pch_enable(device_t dev); #endif int pch_silicon_revision(void); diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2ce9072..8797f09 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -327,8 +327,8 @@ static int smm_handler_copied = 0;
static void smm_install(void) { - device_t dev = PCI_DEV(0, 0, 0); - device_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1); + pci_devfn_t dev = PCI_DEV(0, 0, 0); + pci_devfn_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1); u32 smm_base = 0xa0000; struct ied_header ied = { .signature = "INTEL RSVD", diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 019e6db..4081dae 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -264,7 +264,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 7ba2e88..ba50e3b 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -27,7 +27,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index d328ef6..c5388c4 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -42,7 +42,7 @@ * The BAR will be re-assigned during device * enumeration so these are only temporary. */ -static void enable_usb_bar_on_device(device_t dev, u32 bar) +static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { u32 cmd; pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 5ee7cd9..df7e566 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -48,6 +48,9 @@ * Bus 0:Device 20:Function 0 xHCI Controller */
+#include <device/device.h> +#include <rules.h> + /* PCH types */ #define PCH_TYPE_LPT 0x8c #define PCH_TYPE_LPT_LP 0x9c @@ -91,8 +94,11 @@
#ifndef __ACPI__
-#if defined (__SMM__) && !defined(__ASSEMBLER__) +#if ENV_SMM void intel_pch_finalize_smm(void); +#endif + +#if ENV_RAMSTAGE void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ); void usb_ehci_disable(device_t dev); void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); @@ -187,8 +193,7 @@ void set_gpio(int gpio_num, int value); /* Return non-zero if gpio is set to native function. 0 otherwise. */ int gpio_is_native(int gpio_num);
-#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> +#if ENV_RAMSTAGE #include <arch/acpi.h> #include "chip.h" void pch_enable(device_t dev); @@ -198,7 +203,7 @@ void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); #if CONFIG_ELOG void pch_log_state(void); -#endif +#endif /* CONFIG_ELOG */ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
@@ -210,7 +215,7 @@ void southbridge_clear_smi_status(void); * SMIs. They are split so that other work between the 2 actions. */ void southbridge_smm_clear_state(void); void southbridge_smm_enable_smi(void); -#else +#else /* !ENV_RAMSTAGE */ void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); @@ -218,7 +223,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); -#endif /* !__PRE_RAM__ && !__SMM__ */ +#endif /* ENV_RAMSTAGE */ #endif /* __ASSEMBLER__ */
#define MAINBOARD_POWER_OFF 0 diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 78b89de..0c949ea 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -326,7 +326,7 @@ static int ck804_early_setup_x(void)
for (i = 0; i < 4; i++) { u32 id; - device_t dev; + pci_devfn_t dev; if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); else diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c index e0f8648..e5d0551 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -36,7 +36,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_SMB), 0); diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@
static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 2e03d6b..08abc76 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -116,7 +116,7 @@ static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, { u32 tgio_ctrl, pll_ctrl, dword; int i; - device_t dev; + pci_devfn_t dev;
dev = PCI_DEV(busnx, devnx + 1, 1);
@@ -372,7 +372,7 @@ static int mcp55_early_setup_x(void) busnx = ht_c_index * HT_CHAIN_BUSN_D; for (devnx = 0; devnx < 0x20; devnx++) { u32 id; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(busnx, devnx, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); if(id == 0x036910de) { diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c index 6be8485..c8f556b 100644 --- a/src/southbridge/nvidia/mcp55/early_smbus.c +++ b/src/southbridge/nvidia/mcp55/early_smbus.c @@ -29,7 +29,7 @@
static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
if (dev == PCI_DEV_INVALID) diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@
static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev;
/* Find the device. */ dev = pci_locate_device_on_bus( diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index b766bd7..5326841 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -148,9 +148,9 @@ void smbus_write_byte(u8 dimm, u8 offset, u8 data)
#define PSONREADY_TIMEOUT 0x7fffffff
-static device_t get_vt8237_lpc(void) +static pci_devfn_t get_vt8237_lpc(void) { - device_t dev; + pci_devfn_t dev;
/* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, @@ -173,7 +173,7 @@ static device_t get_vt8237_lpc(void) */ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; int loops;
/* Power management controller */ @@ -262,7 +262,7 @@ void smbus_fixup(const struct mem_controller *ctrl)
void vt8237_sb_enable_fid_vid(void) { - device_t dev, devctl; + pci_devfn_t dev, devctl; u16 devid;
/* Power management controller */ @@ -319,7 +319,7 @@ void vt8237_sb_enable_fid_vid(void)
void enable_rom_decode(void) { - device_t dev; + pci_devfn_t dev;
/* Power management controller */ dev = get_vt8237_lpc(); @@ -332,7 +332,7 @@ void enable_rom_decode(void)
int acpi_get_sleep_type(void) { - device_t dev; + pci_devfn_t dev; u16 tmp;
printk(BIOS_DEBUG, "IN TEST WAKEUP\n"); @@ -357,7 +357,7 @@ int acpi_get_sleep_type(void) #if defined(__GNUC__) void vt8237_early_spi_init(void) { - device_t dev; + pci_devfn_t dev; volatile u16 *spireg; u32 tmp;
@@ -414,7 +414,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom) { struct vt8237_network_rom n; int i, loops; - device_t dev; + pci_devfn_t dev; u32 tmp; u8 status; u16 *rom_write;