Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61457 )
Change subject: soc/intel/tigerlake: Choose PMC IPC to disable HECI1 ......................................................................
soc/intel/tigerlake: Choose PMC IPC to disable HECI1
This patch allows common CSE block to make HECI1 function disable using PMC IPC command `0xA9`.
Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config on tigerlake to perform heci1 disabling using PMC IPC.
Additionally, drop HECI_DISABLE_USING_SMM config from TGL SoC as heci1 disabling using PMC IPC can operate outside SMM.
BUG=none TEST=None
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/smihandler.c 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61457/1
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3ef1005..b9f53ce 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -60,6 +60,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 @@ -82,7 +83,6 @@ select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM
config MAX_CPUS int diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 843733f..5907e5c 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -16,7 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); }