[coreboot-gerrit] [M] Change in coreboot[main]: cpu/via: Implement cache as RAM

[Nico Huber (Code Review)]

Attention is currently required from: Angel Pons, Nico Huber.

Hello Angel Pons, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/82766?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)

Change subject: cpu/via: Implement cache as RAM
......................................................................

cpu/via: Implement cache as RAM

The overall procedure is taken from the original code that was removed
in commit 4c38ed3c38ac (cpu/via/nano: Drop support). Boilerplate at the
start and end was updated (expect timestamp and BIST result in `xmm*'
registers), stack is aligned to 16B, and linker symbols are now used
for the CAR and cached XIP ranges.

Change-Id: Ia190a3006fe897861b7b8a64d47e588871120dd1
Signed-off-by: Nico Huber 
---
M src/cpu/via/c7/Kconfig
M src/cpu/via/car/cache_as_ram.S
2 files changed, 161 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/82766/2