Attention is currently required from: Jérémy Compostella, Subrata Banik.
Hello Jérémy Compostella, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84174?usp=email
to look at the new patch set (#9).
Change subject: src/include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro
......................................................................
src/include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro
Details:
- Add (TM1_TM2_EMTTM_ENABLE_BIT) - Offset 0x1a0 required bits
- Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 0x1b2 required bits
Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b
Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com
---
M src/include/cpu/x86/msr.h
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84174/9
--
To view, visit
https://review.coreboot.org/c/coreboot/+/84174?usp=email
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b
Gerrit-Change-Number: 84174
Gerrit-PatchSet: 9
Gerrit-Owner: Saurabh Mishra
mishra.saurabh@intel.com
Gerrit-Reviewer: Jérémy Compostella
jeremy.compostella@intel.com
Gerrit-Reviewer: Subrata Banik
subratabanik@google.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Balaji Manigandan
balaji.manigandan@intel.com
Gerrit-CC: Hannah Williams
hannah.williams@intel.com
Gerrit-CC: Sanju Jose Thottan
sanjujose.thottan@intel.com
Gerrit-CC: Saurabh Mishra
mishra.saurabh@intel.corp-partner.google.com
Gerrit-Attention: Subrata Banik
subratabanik@google.com
Gerrit-Attention: Jérémy Compostella
jeremy.compostella@intel.com