Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5164
-gerrit
commit 4924914b3b40aca7d1fcada0a6800aa444377e48 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat Feb 8 16:01:11 2014 +0100
Revert "MTRR: Mark all prefetchable resources as WRCOMB."
This reverts commit 30fe6120ca8d7211f0055e47d3ecd569a628f2aa.
Commit resulted with broken RTL8168 ethernet on samsung/lumpy, with errors like this in dmesg: [ 3.725703] r8169 0000:02:00.0 eth0: rtl_eriar_cond == 1 (loop: 100, delay: 100).
Core issue is RTL8168 PCI function rev 06 reporting both its MMIO BARs as prefetchable.
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168 PCI Express Gigabit Ethernet controller (rev 06) Subsystem: Realtek Semiconductor Co., Ltd. RTL8111/8168 PCI Express Gigabit Ethernet controller Flags: bus master, fast devsel, latency 0, IRQ 42 I/O ports at 1000 [size=256] Memory at e0504000 (64-bit, prefetchable) [size=4K] Memory at e0500000 (64-bit, prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: r8169
I found lspci for rev 0c with first MMIO BAR as 64-bit, non-prefetchable.
Change-Id: I83aabddd806ff3615d3d6451c462a2de9d5ab781 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/arch/x86/Kconfig | 8 ++++++++ src/cpu/x86/mtrr/mtrr.c | 5 +++-- src/include/device/resource.h | 1 + src/mainboard/google/bolt/Kconfig | 1 + src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/link/Kconfig | 1 + src/mainboard/google/peppy/Kconfig | 1 + src/mainboard/google/rambi/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/intel/wtm2/Kconfig | 1 + src/northbridge/intel/haswell/gma.c | 19 ++++++++++++++++++- src/northbridge/intel/nehalem/gma.c | 3 +++ src/northbridge/intel/sandybridge/gma.c | 19 ++++++++++++++++++- 13 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 8854e6b..0a21fcc 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -7,6 +7,14 @@ config X86_ARCH_OPTIONS select HAVE_ARCH_MEMCPY select HAVE_ARCH_MEMMOVE
+config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dfb9c94..cdaa791 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -178,8 +178,9 @@ static struct memranges *get_physical_address_space(void) MTRR_TYPE_UNCACHEABLE);
/* Handle any write combining resources. Only prefetchable - * resources are appropriate for this MTRR type. */ - match = IORESOURCE_PREFETCH; + * resources with the IORESOURCE_WRCOMB flag are appropriate + * for this MTRR type. */ + match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; mask |= match; memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 2d64c80..4bd9698 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,6 +21,7 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ +#define IORESOURCE_WRCOMB 0x00100000 /* Write combining resource. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 5247070..1d2b259 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR
config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index d800206..b372c47 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index efe9519..d1e809e 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT + select MARK_GRAPHICS_MEM_WRCOMB
config MAINBOARD_DIR string diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 6cac476..7a406e1 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR
config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 292d321..4d149c9 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select CHROMEOS + select MARK_GRAPHICS_MEM_WRCOMB
config MAINBOARD_DIR string diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 6980234..065830a 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 8e13108..99ed53c 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 2ceffe4..00d7583 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -429,12 +429,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } }
+static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, };
static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 2f13a6b..c7a0e9b 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -703,6 +703,9 @@ static void gma_read_resources(struct device *dev) 0xd0000001); pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + res->flags |= IORESOURCE_WRCOMB; +#endif res->base = (resource_t) 0xd0000000; res->size = (resource_t) 0x10000000; } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index b9a07a2..853139e 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -664,12 +664,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } }
+static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, };
static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,