Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19365 )
Change subject: sb/nvidia/mcp55: Link early_ctrl.c ......................................................................
sb/nvidia/mcp55: Link early_ctrl.c
Change-Id: I3a55c2e8077fdb10768df287f38efcd5e2e64bdf Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/19365 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/tyan/s2912/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/southbridge/nvidia/mcp55/Makefile.inc M src/southbridge/nvidia/mcp55/early_ctrl.c 15 files changed, 8 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 69351ed..4fe8db9 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -62,7 +62,6 @@ return smbus_read_byte(device, address); }
-#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index cdd6d43..a194ccd 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -67,7 +67,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
-#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include <northbridge/amd/amdk8/f.h> diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index e961e0d..1ae6c64 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -61,7 +61,6 @@ return smbus_read_byte(device, address); }
-#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index fbc362b..b497730 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -70,7 +70,6 @@ return smbus_read_byte(device, address); }
-#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 2f191ee..4acb240 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -42,7 +42,6 @@ #include <arch/early_variables.h> #include <cbmem.h> #include <southbridge/nvidia/mcp55/mcp55.h> -#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index c11d083..c0894b9 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -60,7 +60,6 @@ return smbus_read_byte(device, address); }
-#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 5641adb..b401d1b 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -59,7 +59,6 @@ return smbus_read_byte(device, address); }
-#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 5316a84..52a62c3 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -69,7 +69,6 @@ return smbus_read_byte(device, address); }
-#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 9f4a3bb..ac8d61e 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -61,7 +61,6 @@ return smbus_read_byte(device, address); }
-#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 22c5fd4..d457f1b 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -43,7 +43,6 @@ #include <cbmem.h>
#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN -#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index e97af8a..26f3da7 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -42,7 +42,6 @@ #include <arch/early_variables.h> #include <cbmem.h> #include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN -#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 9bbd139..6888bf6 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -60,7 +60,6 @@ return smbus_read_byte(device, address); }
-#include "southbridge/nvidia/mcp55/early_ctrl.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 054e143..4c8c19f 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -42,7 +42,6 @@ #include <arch/early_variables.h> #include <cbmem.h> #include <southbridge/nvidia/mcp55/mcp55.h> -#include "southbridge/nvidia/mcp55/early_ctrl.c"
#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 9b1e133..7073b69 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -20,6 +20,7 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c +romstage-y += early_ctrl.c
ifeq ($(CONFIG_MCP55_USE_AZA),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index dabf7ad..1f80316 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -15,7 +15,14 @@ * GNU General Public License for more details. */
+#include <arch/io.h> +#include <console/console.h> #include <reset.h> +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8) +#include <northbridge/amd/amdk8/amdk8.h> +#else /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ +#include <northbridge/amd/amdfam10/amdfam10.h> +#endif #include "mcp55.h"
void soft_reset(void)