Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19545 )
Change subject: sb/intel/bd82x6x/finalize: Use register name ......................................................................
sb/intel/bd82x6x/finalize: Use register name
Use register name instead of hex values.
No functional change.
Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d Signed-off-by: Patrick Rudolph siro@das-labor.org Reviewed-on: https://review.coreboot.org/19545 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Sumeet R Pawnikar sumeet.r.pawnikar@intel.com --- M src/southbridge/intel/bd82x6x/finalize.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 3 insertions(+), 2 deletions(-)
Approvals: Sumeet R Pawnikar: Looks good to me, approved Arthur Heymans: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index c9296fd..4e08fc6 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -60,10 +60,10 @@ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */ - pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, 1 << 4);
/* GEN_PMCON Lock */ - pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2));
/* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 8b22fca..da1f901 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -140,6 +140,7 @@ #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 +#define GEN_PMCON_LOCK 0xa6 #define ETR3 0xac #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20)