Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79025?usp=email )
Change subject: nb/intel/haswell: Move SPD addresses to devicetree ......................................................................
nb/intel/haswell: Move SPD addresses to devicetree
Introduce a sandybridge-style devicetree setting for SPD addresses, and use it instead of runtime code in mb_get_spd_map() for all haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all boards except google/slippy.
Patch also covers recently added Z97 boards using Broadwell MRC.
Also update util/autoport to match.
abuild passes for all affected boards. autoport builds, but otherwise untested.
Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34 Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb M src/mainboard/asrock/fatal1ty_z87_professional/romstage.c M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/asrock/z87e-itx/devicetree.cb M src/mainboard/asrock/z87e-itx/romstage.c M src/mainboard/asrock/z87m_oc_formula/devicetree.cb M src/mainboard/asrock/z87m_oc_formula/romstage.c M src/mainboard/asrock/z97_extreme6/devicetree.cb M src/mainboard/asrock/z97_extreme6/romstage.c M src/mainboard/asrock/z97e-itx_ac/devicetree.cb M src/mainboard/asrock/z97e-itx_ac/romstage.c M src/mainboard/dell/e7240/devicetree.cb M src/mainboard/dell/e7240/romstage.c M src/mainboard/dell/optiplex_9020/devicetree.cb M src/mainboard/dell/optiplex_9020/romstage.c M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/beltino/romstage.c M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/hp/folio_9480m/romstage.c M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/haswell/romstage.c M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/romstage.c M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/romstage.c M src/mainboard/msi/h81m-p33/devicetree.cb M src/mainboard/msi/h81m-p33/romstage.c M src/mainboard/supermicro/x10slm-f/devicetree.cb M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/Makefile.mk M src/northbridge/intel/haswell/broadwell_mrc/raminit.c M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c M src/northbridge/intel/haswell/raminit.h A src/northbridge/intel/haswell/raminit_shared.c M util/autoport/haswell.go M util/autoport/lynxpoint.go 42 files changed, 43 insertions(+), 145 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index e9a9876..4cd3b3c 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -3,6 +3,7 @@ # This mainboard has VGA register "gpu_ddi_e_connected" = "1"
+ register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 25b157d..1c85a29 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -16,14 +15,6 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb index 5fbc99f..5b20f3c 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb +++ b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/haswell + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c b/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c index 44932e7..d2a8680 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c +++ b/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c @@ -1,21 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) { }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_FLEX }, diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index d84c471..b4fe343 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -2,6 +2,7 @@
chip northbridge/intel/haswell register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0, 0x52, 0}"
chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3573d69..31c5d71 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -16,12 +15,6 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, diff --git a/src/mainboard/asrock/z87e-itx/devicetree.cb b/src/mainboard/asrock/z87e-itx/devicetree.cb index 32883e4..dcc7d52 100644 --- a/src/mainboard/asrock/z87e-itx/devicetree.cb +++ b/src/mainboard/asrock/z87e-itx/devicetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/haswell + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/asrock/z87e-itx/romstage.c b/src/mainboard/asrock/z87e-itx/romstage.c index b50390e..d2a8680 100644 --- a/src/mainboard/asrock/z87e-itx/romstage.c +++ b/src/mainboard/asrock/z87e-itx/romstage.c @@ -1,19 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) { }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_FLEX }, diff --git a/src/mainboard/asrock/z87m_oc_formula/devicetree.cb b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb index cbde4cb..3b56340 100644 --- a/src/mainboard/asrock/z87m_oc_formula/devicetree.cb +++ b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb @@ -2,6 +2,7 @@
chip northbridge/intel/haswell register "gpu_dp_c_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
chip cpu/intel/haswell device cpu_cluster 0 on diff --git a/src/mainboard/asrock/z87m_oc_formula/romstage.c b/src/mainboard/asrock/z87m_oc_formula/romstage.c index 44932e7..d2a8680 100644 --- a/src/mainboard/asrock/z87m_oc_formula/romstage.c +++ b/src/mainboard/asrock/z87m_oc_formula/romstage.c @@ -1,21 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) { }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_FLEX }, diff --git a/src/mainboard/asrock/z97_extreme6/devicetree.cb b/src/mainboard/asrock/z97_extreme6/devicetree.cb index 2258a1b..dcb8123 100644 --- a/src/mainboard/asrock/z97_extreme6/devicetree.cb +++ b/src/mainboard/asrock/z97_extreme6/devicetree.cb @@ -8,6 +8,7 @@ # This mainboard has a DP output register "gpu_dp_c_hotplug" = "7"
+ register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/asrock/z97_extreme6/romstage.c b/src/mainboard/asrock/z97_extreme6/romstage.c index a344dee..35aece9 100644 --- a/src/mainboard/asrock/z97_extreme6/romstage.c +++ b/src/mainboard/asrock/z97_extreme6/romstage.c @@ -1,21 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) { }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ diff --git a/src/mainboard/asrock/z97e-itx_ac/devicetree.cb b/src/mainboard/asrock/z97e-itx_ac/devicetree.cb index 2f118db..43602d4 100644 --- a/src/mainboard/asrock/z97e-itx_ac/devicetree.cb +++ b/src/mainboard/asrock/z97e-itx_ac/devicetree.cb @@ -3,6 +3,7 @@ register "gpu_dp_b_hotplug" = "4" register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0, 0x52, 0}"
chip cpu/intel/haswell device cpu_cluster 0 on diff --git a/src/mainboard/asrock/z97e-itx_ac/romstage.c b/src/mainboard/asrock/z97e-itx_ac/romstage.c index 4abce7b..3919e99 100644 --- a/src/mainboard/asrock/z97e-itx_ac/romstage.c +++ b/src/mainboard/asrock/z97e-itx_ac/romstage.c @@ -1,19 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) { }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_FLEX }, diff --git a/src/mainboard/dell/e7240/devicetree.cb b/src/mainboard/dell/e7240/devicetree.cb index c408383..ee5f1ab 100644 --- a/src/mainboard/dell/e7240/devicetree.cb +++ b/src/mainboard/dell/e7240/devicetree.cb @@ -2,6 +2,7 @@
chip northbridge/intel/haswell register "ec_present" = "true" + register "spd_addresses" = "{0x50, 0, 0x52, 0}"
chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/dell/e7240/romstage.c b/src/mainboard/dell/e7240/romstage.c index 6b2cb7a8..c439bfc 100644 --- a/src/mainboard/dell/e7240/romstage.c +++ b/src/mainboard/dell/e7240/romstage.c @@ -2,7 +2,6 @@
#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -17,12 +16,6 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* dock left */ diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb index 841285b..223831c 100644 --- a/src/mainboard/dell/optiplex_9020/devicetree.cb +++ b/src/mainboard/dell/optiplex_9020/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/haswell # This mainboard has VGA register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c index 8198eb0..b9aae99 100644 --- a/src/mainboard/dell/optiplex_9020/romstage.c +++ b/src/mainboard/dell/optiplex_9020/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -15,14 +14,6 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA); }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP}, diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 9dacd6d..95b04ed 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -13,6 +13,7 @@
register "usb_xhci_on_resume" = "true"
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index ecf5490..8604423 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -39,12 +38,6 @@ RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: VP8 */ diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index 6a8e919..e47e682 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -13,6 +13,7 @@ .backlight_pwm_hz = 200, }" register "usb_xhci_on_resume" = "true" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c index fa7cba1..3b63629 100644 --- a/src/mainboard/hp/folio_9480m/romstage.c +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -16,12 +15,6 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */ diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 3226170..cd2c84e 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -11,6 +11,7 @@ # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
+ register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 936703b..0963eb80 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -40,14 +39,6 @@ RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ diff --git a/src/mainboard/lenovo/haswell/romstage.c b/src/mainboard/lenovo/haswell/romstage.c index 9b9a15f..518bd4b 100644 --- a/src/mainboard/lenovo/haswell/romstage.c +++ b/src/mainboard/lenovo/haswell/romstage.c @@ -2,7 +2,6 @@
#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <option.h> #include <ec/lenovo/pmh7/pmh7.h> diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index f8467c7..10e23b3 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -13,6 +13,7 @@ .backlight_pwm_hz = 220, }" register "ec_present" = "true" + register "spd_addresses" = "{0x50, 0, 0x51, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/lenovo/haswell/variants/t440p/romstage.c b/src/mainboard/lenovo/haswell/variants/t440p/romstage.c index f158716..84ddb5b 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/romstage.c +++ b/src/mainboard/lenovo/haswell/variants/t440p/romstage.c @@ -1,16 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x51; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */ diff --git a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb index 0d705fb..815d3fa 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb @@ -13,6 +13,7 @@ .backlight_pwm_hz = 220, }" register "ec_present" = "true" + register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/lenovo/haswell/variants/w541/romstage.c b/src/mainboard/lenovo/haswell/variants/w541/romstage.c index a410f56..69854db 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/romstage.c +++ b/src/mainboard/lenovo/haswell/variants/w541/romstage.c @@ -2,19 +2,10 @@
#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <ec/lenovo/pmh7/pmh7.h> #include <device/pci_ops.h>
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x52; - spdi->addresses[2] = 0x51; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb index f72ed9f..6051ca6 100644 --- a/src/mainboard/msi/h81m-p33/devicetree.cb +++ b/src/mainboard/msi/h81m-p33/devicetree.cb @@ -2,6 +2,7 @@
chip northbridge/intel/haswell register "gpu_ddi_e_connected" = "1" + register "spd_addresses" = "{0x50, 0, 0x52, 0}" chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end end diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c index f4db2644..1c85a29 100644 --- a/src/mainboard/msi/h81m-p33/romstage.c +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -16,12 +15,6 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[2] = 0x52; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 8625daa..479de3f 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/haswell + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
chip cpu/intel/haswell device cpu_cluster 0 on ops haswell_cpu_bus_ops end diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 01dab69..d4609c8 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -16,14 +15,6 @@ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); }
-void mb_get_spd_map(struct spd_info *spdi) -{ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_INTERNAL }, diff --git a/src/northbridge/intel/haswell/Makefile.mk b/src/northbridge/intel/haswell/Makefile.mk index 8da72dc..bc8cf42 100644 --- a/src/northbridge/intel/haswell/Makefile.mk +++ b/src/northbridge/intel/haswell/Makefile.mk @@ -16,6 +16,7 @@ romstage-y += romstage.c romstage-y += early_init.c romstage-y += report_platform.c +romstage-y += raminit_shared.c
postcar-y += memmap.c
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index 0bb6f28..1ed42485 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -374,9 +374,8 @@ /* Broadwell MRC uses ACPI values for boot_mode */ pei_data.boot_mode = s3resume ? ACPI_S3 : ACPI_S0;
- /* Obtain the SPD addresses from mainboard code */ struct spd_info spdi = {0}; - mb_get_spd_map(&spdi); + get_spd_info(&spdi, cfg);
/* * Read the SPDs over SMBus in coreboot code so that the data can be used to diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 274e549..dc71340 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -39,6 +39,8 @@ bool usb_xhci_on_resume;
struct i915_gpu_controller_info gfx; + + u8 spd_addresses[4]; };
#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */ diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 52bb3b1..9a7b7fe 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -391,9 +391,8 @@ /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ pei_data.boot_mode = s3resume ? 2 : 0;
- /* Obtain the SPD addresses from mainboard code */ struct spd_info spdi = {0}; - mb_get_spd_map(&spdi); + get_spd_info(&spdi, cfg);
/* MRC expects left-aligned SMBus addresses, and 0xff for memory-down */ for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) { diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c index eff9938..c53ea12 100644 --- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c +++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/dram/ddr3.h> #include <device/smbus_host.h> +#include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <string.h> @@ -70,8 +71,9 @@
static void get_spd_data(struct sysinfo *ctrl) { + const struct northbridge_intel_haswell_config *cfg = config_of_soc(); struct spd_info spdi = {0}; - mb_get_spd_map(&spdi); + get_spd_info(&spdi, cfg); const uint8_t *cbfs_spd = get_spd_data_from_cbfs(&spdi); for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index e151b46..6c76739 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -4,6 +4,7 @@ #define NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H
#include <types.h> +#include "chip.h"
#define SPD_MEMORY_DOWN 0xff
@@ -15,6 +16,7 @@ /* Mainboard callback to fill in the SPD addresses */ void mb_get_spd_map(struct spd_info *spdi);
+void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg); void perform_raminit(const int s3resume);
#endif /* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */ diff --git a/src/northbridge/intel/haswell/raminit_shared.c b/src/northbridge/intel/haswell/raminit_shared.c new file mode 100644 index 0000000..90fe114 --- /dev/null +++ b/src/northbridge/intel/haswell/raminit_shared.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include "chip.h" +#include "raminit.h" + +void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg) +{ + if (CONFIG(HAVE_SPD_IN_CBFS)) { + /* With memory down: from mainboard code */ + mb_get_spd_map(spdi); + } else { + /* Without memory down: from devicetree */ + memcpy(spdi->addresses, cfg->spd_addresses, ARRAY_SIZE(spdi->addresses)); + } +} diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go index 588d271..668771b 100644 --- a/util/autoport/haswell.go +++ b/util/autoport/haswell.go @@ -65,6 +65,7 @@ "usb_xhci_on_resume": "false", /* FIXME:XX hardcoded. */ "gfx": "GMA_STATIC_DISPLAYS(0)", + "spd_addresses": "{0x50, 0x51, 0x52, 0x53}" # FIXME: Put proper SPD map here", }, Children: []DevTreeNode{ { diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go index 98a1ca8..7168686 100644 --- a/util/autoport/lynxpoint.go +++ b/util/autoport/lynxpoint.go @@ -272,7 +272,6 @@ Add_gpl(sb) sb.WriteString(`#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void) @@ -284,15 +283,6 @@ { }
-void mb_get_spd_map(struct spd_info *spdi) -{ - /* FIXME: check this */ - spdi->addresses[0] = 0x50; - spdi->addresses[1] = 0x51; - spdi->addresses[2] = 0x52; - spdi->addresses[3] = 0x53; -} - const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ /* Length, Enable, OCn#, Location */