[coreboot-gerrit] Change in coreboot[master]: arch/x86: Define `postcar_frame_add_cbmem_top`

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45926 )

Change subject: arch/x86: Define `postcar_frame_add_cbmem_top`
......................................................................

arch/x86: Define `postcar_frame_add_cbmem_top`

This function is to be used to cache a region below cbmem_top().

Change-Id: I3eab4e55c3670094e32ba86550c3d602c0bbef07
Signed-off-by: Angel Pons 
---
M src/arch/x86/include/arch/romstage.h
M src/arch/x86/postcar_loader.c
2 files changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/45926/1

diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h
index 28d29bf..cb4aa73 100644
--- a/src/arch/x86/include/arch/romstage.h
+++ b/src/arch/x86/include/arch/romstage.h
@@ -33,6 +33,10 @@
  */
 void postcar_frame_add_mtrr(struct postcar_frame *pcf,
    			uintptr_t addr, size_t size, int type);
+/*
+ * Add variable MTRR covering the given down-aligned size below cbmem_top().
+ */
+void postcar_frame_add_cbmem_top(struct postcar_frame *pcf, size_t size, uintptr_t alignment);

/*
  * Add variable MTRR covering the memory-mapped ROM with given MTRR type.
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index 241ba8c..366f378 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -153,6 +153,13 @@
    stage_cache_add(STAGE_POSTCAR, prog);
 }

+void postcar_frame_add_cbmem_top(struct postcar_frame *pcf, size_t size, uintptr_t alignment)
+{
+	uintptr_t top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), alignment);
+
+	postcar_frame_add_mtrr(pcf, top_of_ram - size, size, MTRR_TYPE_WRBACK);
+}
+
 /*
  * Cache the TSEG region at the top of ram. This region is
  * not restricted to SMM mode until SMM has been relocated.