[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Configure 9 I/O for ADL-N

[Angel Pons (Code Review)]

Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Krishna P Bhat D, Usha P, Patrick Rudolph, Kangheui Won.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59752 )

Change subject: soc/intel/alderlake: Configure 9 I/O for ADL-N
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Patch Set 2: Code-Review+1

(1 comment)

Commit Message:

PS2: 
I'd squash CB:59751 into this change. It doesn't make sense to have the `SOC_INTEL_ALDERLAKE_PCH_N` option without the correct settings. I'd rewrite the commit message as follows:

soc/intel/alderlake: Add support for ADL-N

Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and
 use it to specify the correct amount of PCIe I/O. Document number
 645548 indicates that Alder Lake-N has 9 PCH root ports, no CPU
 root ports, 5 clock sources and 5 clock request signals.

I don't know if the numbers are correct. If they aren't, just adapt this accordingly.