Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )
Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
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Patch Set 43:
(1 comment)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/512b05f7_48010e91?usp... :
PS17, Line 54: .port = PID_GPIOCOM0,
sorry. my bad. typo Subrata:) […]
For constructing PCR addresses to access the register, 8-bit port id is used. When accessing from outside of PCD, 16bit is used the first byte is segment ID, followed by 8bit port id. For instance, for IOM to access GPIO registers, segment ID is needed for global routing, who's value is 0xf2. The 2nd set of PID defines is needed for cpu_port:
#define SEGMENTID_CHIPSET0 0xf2
#define PID16_CHIPSET0(x) ((SEGMENTID_CHIPSET0 << 8) | x)
#define PID16_GPIOCOM0 PID16_CHIPSET0(PID_GPIOCOM0)
#define PID16_GPIOCOM1 PID16_CHIPSET0(PID_GPIOCOM1)
#define PID16_GPIOCOM3 PID16_CHIPSET0(PID_GPIOCOM3)
#define PID16_GPIOCOM4 PID16_CHIPSET0(PID_GPIOCOM4)
#define PID16_GPIOCOM5 PID16_CHIPSET0(PID_GPIOCOM5)
The field has been changed in the typec AUX bias cntrl registers in PTL. The port id is now 16-bit.
15:0 RW 0x0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 RW 0x0 BIT_NUM Data bit Position in PCH GPIO
31:24 RW 0x0 VW_INDEX VW Index in PCH GPIO
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