Tobias Diedrich (ranma+coreboot@tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12796
-gerrit
commit d1db2d4600d9a20d202f53918d392f0770375d48 Author: Tobias Diedrich ranma+coreboot@tdiedrich.de Date: Wed Dec 23 23:27:06 2015 +0100
pcengines/apu1: Supply TPM modules on the LPC connector
Since the APU1 has an LPC connector it is possible to connect a TPM. I'm using mine mostly for the HWRNG which the APU1 lacks.
This takes care of setting up the TPM interrupt. Interrupt 5 was chosen since it is not otherwise used on the APU1, Alternatively 1, 7, 10-11 and 14-15 should be available as well. It may also be possible to share the ACPI interrupt (9).
Previously I was getting frequent "genirq: Flags mismatch irq 4. 00000000 (serial) vs. 00000080 (tpm0)" errors.
With this I also no longer need to use "tpm_tis.force=1" on the kernel commandline since the TPM is now declared in the ACPI DSDT.
See also https://plus.google.com/+TobiasDiedrich/posts/cRv9MwrCdEa and https://plus.google.com/+TobiasDiedrich/posts/BDnJLGFMW8o
Change-Id: Ie732228471f6c40d77e17cbed34726961b1fcddd Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de --- src/mainboard/pcengines/apu1/Kconfig | 14 ++++++++++++++ src/mainboard/pcengines/apu1/devicetree.cb | 7 +++++++ src/mainboard/pcengines/apu1/dsdt.asl | 10 ++++++++++ 3 files changed, 31 insertions(+)
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 2328776..2263810 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -30,6 +30,20 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 select SPD_CACHE + select MAINBOARD_HAS_LPC_TPM if ENABLE_LPC_TPM_SUPPORT + select LPC_TPM if ENABLE_LPC_TPM_SUPPORT + +config ENABLE_LPC_TPM_SUPPORT + bool + default n + prompt "Support TPM modules on the APU1 LPC connector" + help + Enable this option to enable LPC TPM support for the APU1. + + To use a TPM module with the APU1 you must make sure that + the third-party module matches the connector pinout. + + If unsure, say N.
config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 72e89c0..d69b0fd 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -43,6 +43,13 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.1 off end # IDE 0x439c device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d +#ifdef CONFIG_ENABLE_LPC_TPM_SUPPORT + chip drivers/pc80/tpm + device pnp 0c31.0 on + irq 0x70 = 5 + end + end +#endif chip superio/nuvoton/nct5104d register "irq_trigger_type" = "0" device pnp 2e.0 off end diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index bd9dff2..1b0c0f5 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -47,6 +47,16 @@ DefinitionBlock ( } } /* End Scope(_SB) */
+#ifdef CONFIG_ENABLE_LPC_TPM_SUPPORT + /* + * LPC Trusted Platform Module + */ + Scope (_SB.PCI0.LIBR) + { + #include <drivers/pc80/tpm/acpi/tpm.asl> + } +#endif + /* Contains the supported sleep states for this chipset */ #include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>