Attention is currently required from: Tarun Tuli, Lean Sheng Tan.
Hello build bot (Jenkins), Sean Rhodes, Tarun Tuli, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/73738
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Enable early caching of RAMTOP region ......................................................................
soc/intel/tigerlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.
Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable).
Signed-off-by: Lean Sheng Tan sheng.tan@9elements.com Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/73738/2