Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84174?usp=email )
Change subject: include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro ......................................................................
include/cpu/x86: Add Misc Enable and Thermal Interrupt Register Macro
Details: - Add (TM1_TM2_EMTTM_ENABLE_BIT) - Offset 0x1a0 required bits - Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 0x1b2 required bits
Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/84174 Reviewed-by: Subrata Banik subratabanik@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com --- M src/include/cpu/x86/msr.h 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: Subrata Banik: Looks good to me, approved Pratikkumar V Prajapati: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index d369972..a5226fb 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -48,6 +48,7 @@ #define IA32_THERM_INTERRUPT 0x19b #define IA32_MISC_ENABLE 0x1a0 #define FAST_STRINGS_ENABLE_BIT (1 << 0) +#define TM1_TM2_EMTTM_ENABLE_BIT (1 << 3) #define SPEED_STEP_ENABLE_BIT (1 << 16) #define IA32_ENERGY_PERF_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 @@ -55,6 +56,7 @@ #define ENERGY_POLICY_POWERSAVE 15 #define ENERGY_POLICY_MASK 0xf #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 +#define CRITICAL_TEMP_INTERRUPT_ENABLE (1 << 4) #define SMRR_PHYSBASE_MSR 0x1F2 #define SMRR_PHYSMASK_MSR 0x1F3 #define IA32_PLATFORM_DCA_CAP 0x1f8