Attention is currently required from: Felix Held.
Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84380?usp=email )
Change subject: soc/amd/glinda/.../iomap.h: Update for glinda ......................................................................
Patch Set 2:
(5 comments)
This change is ready for review.
File src/soc/amd/glinda/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/84380/comment/f0a3443a_5c709924?usp... : PS1, Line 14: #define GNB_IO_APIC_ADDR 0xfec01000 //TODO
unless this is hardcoded somewhere else (which it shouldn't be), this is correct. […]
Done
https://review.coreboot.org/c/coreboot/+/84380/comment/5e405983_a0484614?usp... : PS1, Line 15: #define SPI_BASE_ADDRESS 0xfec10000 //TODO
this is still used ass the spi mmio base
Done
https://review.coreboot.org/c/coreboot/+/84380/comment/1c7cf4bd_bccf763d?usp... : PS1, Line 18: #define ALINK_AHB_ADDRESS 0xfedc0000 //TODO Its not in the table anymore (maybe it moved in the PPR)
that one is still there
I take your word for it, since I can't find it.
https://review.coreboot.org/c/coreboot/+/84380/comment/8a57cf5a_f322d032?usp... : PS1, Line 33: #define APU_UART4_BASE 0xfedd1000 //TODO not in the table but used on actual schematics (does it exist or not?)
i see uart0.. […]
I was looking at table 147 in document 57254 (Rev 1.59) and I can't see UART4 there. But maybe the table is outdated.
https://review.coreboot.org/c/coreboot/+/84380/comment/2b47227e_837215e8?usp... : PS1, Line 40: /* I/O Ranges */ : #define ACPI_IO_BASE 0x0400 : #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) : #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) : #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) : #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) : #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) : #define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) : #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) : #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) These are not used anywhere and I also can't find them in the PPR.