Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Shamile Khan, Rajmohan Mani, Patrick Rudolph, Prashant Malani, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41759
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Add Type-C IOM base address and size macro ......................................................................
soc/intel/tigerlake: Add Type-C IOM base address and size macro
This adds Type-C IO Manageability engine base address and size. Tigerlake EDS(#575681) section 3.4.3 describes host bridge REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000. IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16).
BUG=:b:156016218 TEST=Built and booted on Volteer.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 --- M src/soc/intel/tigerlake/include/soc/iomap.h 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41759/3