Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48080 )
Change subject: mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/48080/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48080/4//COMMIT_MSG@12 PS4, Line 12: Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low
Why are these being driven low? Are these the CLK pins?
As per HW team recommendation, this PINs should drive low to get card detected on x1 DT slot
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... PS4, Line 54: free running CLK
Just for my education: What is a free running CLK?
RP8 has CLK6 as source and CLK7 as req. Hence we had asked to configure CLK programming as free running to get the right CLK assigned between CLK6/7.
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/gpio.c:
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... PS4, Line 76: PAD_CFG_GPO
Shouldn't this be NF?
Yes you are right, ideally this has to be NF1 but this is a recommendation/W/A on RVP where we need to drive those signal low to get the card detected
https://review.coreboot.org/c/coreboot/+/48080/4/src/mainboard/intel/adlrvp/... PS4, Line 78: PAD_CFG_GPO
Same here.
-same-