Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9430
-gerrit
commit 4225d9368290324c06fb151cff3aed4e3c81a6b8 Author: Furquan Shaikh furquan@google.com Date: Sat Oct 4 17:00:56 2014 -0700
t132: Add vboot2 support
BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles successfully and boots to kernel prompt using vboot2
Original-Change-Id: Ibf7666d273e4d1af719c60d3f02bddcb4461f4bd Original-Signed-off-by: Furquan Shaikh furquan@google.com Original-Reviewed-on: https://chromium-review.googlesource.com/221576 Original-Tested-by: Furquan Shaikh furquan@chromium.org Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Commit-Queue: Furquan Shaikh furquan@chromium.org
(cherry picked from commit 8335915940ae9ba9e51e360df6963a27b05d6324) Signed-off-by: Aaron Durbin adurbin@chromium.org
Change-Id: I7d3d5cda4c4be945931d9133ab18680dac1dcefe --- src/mainboard/google/rush/memlayout.ld | 2 +- src/mainboard/google/rush_ryu/memlayout.ld | 2 +- src/soc/nvidia/tegra132/Makefile.inc | 14 +++++++ src/soc/nvidia/tegra132/include/soc/memlayout.ld | 44 --------------------- .../nvidia/tegra132/include/soc/memlayout_vboot.ld | 43 ++++++++++++++++++++ .../tegra132/include/soc/memlayout_vboot2.ld | 46 ++++++++++++++++++++++ src/soc/nvidia/tegra132/include/soc/verstage.h | 25 ++++++++++++ src/soc/nvidia/tegra132/verstage.c | 39 ++++++++++++++++++ 8 files changed, 169 insertions(+), 46 deletions(-)
diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld index ead7f47..85f4a97 100644 --- a/src/mainboard/google/rush/memlayout.ld +++ b/src/mainboard/google/rush/memlayout.ld @@ -1 +1 @@ -#include <soc/memlayout.ld> +#include <soc/memlayout_vboot.ld> diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld index ead7f47..85f4a97 100644 --- a/src/mainboard/google/rush_ryu/memlayout.ld +++ b/src/mainboard/google/rush_ryu/memlayout.ld @@ -1 +1 @@ -#include <soc/memlayout.ld> +#include <soc/memlayout_vboot.ld> diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 81d08f5..2806ead 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -21,6 +21,20 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif
+verstage-y += verstage.c +verstage-y += cbfs.c +verstage-y += dma.c +verstage-y += monotonic_timer.c +verstage-y += spi.c +verstage-y += padconfig.c +verstage-y += funitcfg.c +verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +verstage-y += ../tegra/gpio.c +verstage-y += ../tegra/i2c.c +verstage-y += ../tegra/pinmux.c +verstage-y += clock.c +verstage-y += i2c.c + romstage-y += 32bit_reset.S romstage-y += romstage_asm.S romstage-y += addressmap.c diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld deleted file mode 100644 index 63cf4f0..0000000 --- a/src/soc/nvidia/tegra132/include/soc/memlayout.ld +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <memlayout.h> - -#include <arch/header.ld> - -/* - * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, - * so the bootblock loading address must be placed after that. After the - * handoff that area may be reclaimed for other uses, e.g. CBFS cache. - * TODO: Did this change on Tegra132? What's the new valid range? - */ - -SECTIONS -{ - SRAM_START(0x40000000) - /* 16K hole */ - PRERAM_CBMEM_CONSOLE(0x40004000, 8K) - CBFS_CACHE(0x40006000, 88K) - STACK(0x4001C000, 16K) - BOOTBLOCK(0x40020000, 20K) - ROMSTAGE(0x40025000, 108K) - SRAM_END(0x40040000) - - DRAM_START(0x80000000) - RAMSTAGE(0x80200000, 192K) -} diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld new file mode 100644 index 0000000..c097c3c --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot.ld @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, + * so the bootblock loading address must be placed after that. After the + * handoff that area may be reclaimed for other uses, e.g. CBFS cache. + * TODO: Did this change on Tegra132? What's the new valid range? + */ + +SECTIONS +{ + SRAM_START(0x40000000) + PRERAM_CBMEM_CONSOLE(0x40000000, 8K) + CBFS_CACHE(0x40002000, 88K) + STACK(0x40018000, 16K) + BOOTBLOCK(0x4001C000, 20K) + ROMSTAGE(0x40021000, 124K) + SRAM_END(0x40040000) + + DRAM_START(0x80000000) + RAMSTAGE(0x80200000, 192K) +} diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld new file mode 100644 index 0000000..8743268 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> +#include <vendorcode/google/chromeos/memlayout.h> + +#include <arch/header.ld> + +/* + * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, + * so the bootblock loading address must be placed after that. After the + * handoff that area may be reclaimed for other uses, e.g. CBFS cache. + * TODO: Did this change on Tegra132? What's the new valid range? + */ + +SECTIONS +{ + SRAM_START(0x40000000) + PRERAM_CBMEM_CONSOLE(0x40000000, 8K) + CBFS_CACHE(0x40002000, 72K) + VBOOT2_WORK(0x40014000, 16K) + STACK(0x40018000, 8K) + BOOTBLOCK(0x4001A000, 20K) + VERSTAGE(0x4001F000, 60K) + ROMSTAGE(0x4002E000, 72K) + SRAM_END(0x40040000) + + DRAM_START(0x80000000) + RAMSTAGE(0x80200000, 192K) +} diff --git a/src/soc/nvidia/tegra132/include/soc/verstage.h b/src/soc/nvidia/tegra132/include/soc/verstage.h new file mode 100644 index 0000000..6901bc3 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/verstage.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ +#define __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ + +void verstage_mainboard_init(void); + +#endif /* __SOC_NVIDIA_TEGRA132_SOC_VERSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra132/verstage.c b/src/soc/nvidia/tegra132/verstage.c new file mode 100644 index 0000000..ba3e183 --- /dev/null +++ b/src/soc/nvidia/tegra132/verstage.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arch/exception.h> +#include <console/console.h> +#include <soc/verstage.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void __attribute__((weak)) verstage_mainboard_init(void) +{ + /* Default empty implementation. */ +} + +void main(void) +{ + console_init(); + exception_init(); + + verstage_mainboard_init(); + + vboot2_verify_firmware(); +}