Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83911?usp=email )
Change subject: mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configuration ......................................................................
mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configuration
Looking at Intel document 759603 revision 001, Alder Lake N only has 5 PCIe clock outputs and clock request pins. I only have the version 2 of this board which has a significantly different USB port configuration to version 1, but there the Ethernet controller on RP 11 and the E key m.2 slot on RP 12 share the last PCIe clock output. The on-board TUBF0304 clock buffer chip takes the clock output form the last PCH PCIe clock generator output and drives the clock inputs of both the last Ethernet chip and the E key m.2 slot. Since the last clock output is always active, since RP 11 has the PCIE_RP_CLK_REQ_UNUSED flag set, using the non-existent clock output and request for RP 12 didn't break things. ASPM L0s might still work though, since that one doesn't involve switching off the PCIe reference clock, but haven't tested that yet.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I103f7c3fe0b806f5c0a5202b8221f522a4b1c378 --- M src/mainboard/cwwk/adl/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/83911/1
diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb index 0963d8f..7dd95d7 100644 --- a/src/mainboard/cwwk/adl/devicetree.cb +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -42,9 +42,9 @@ }"
register "pch_pcie_rp[PCH_RP(12)]" = "{ - .clk_src = 5, - .clk_req = 5, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .pcie_rp_aspm = ASPM_DISABLE, }"
# Enable EDP in PortA