Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80683?usp=email )
Change subject: soc/intel/xeon_sp: Refactor IOAT compiler optimization outs ......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80683/comment/c30bdf77_81cb3685 : PS3, Line 16: TEST=intel/archercity CRB
Is there a size and/or run-time difference? Please document that.
The patch is merged and let me explain here: There would be a size difference, as below (CPX is used for test),
fallback/ramstage 0x9700 stage 90718 LZMA (199228 decompressed) -> with optimization outs fallback/ramstage 0x9700 stage 90900 LZMA (199488 decompressed) -> without optimization outs
File src/soc/intel/xeon_sp/uncore_acpi.c:
https://review.coreboot.org/c/coreboot/+/80683/comment/c0ded16e_dc808d1a : PS3, Line 339: if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri)) {
Is that pattern common in coreboot?
Yes, we can use this as a common pattern for future IOAT operations as well. For each sites, the size saving is small. But we can follow this as a general practice for consistent code maintenance.