Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43743 )
Change subject: nb/intel/haswell: Enable DMI ASPM ......................................................................
Patch Set 2:
(2 comments)
I checked which steps need to be done on which variants, and updated the code accordingly. I also adjusted some registers' width, and put names to them.
https://review.coreboot.org/c/coreboot/+/43743/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43743/1//COMMIT_MSG@8 PS1, Line 8:
DMI stands for `Direct Media Interface`, which is the PCIe-like link between the SA (System Agent, a […]
Done, I hope.
https://review.coreboot.org/c/coreboot/+/43743/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/northbridge.c:
https://review.coreboot.org/c/coreboot/+/43743/1/src/northbridge/intel/haswe... PS1, Line 452: IOT
I think this has to do with the GDXC thingy, not sure if needed. It's optional.
Dropped as it's not needed.