[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: bootblock: implement platform_prog_run()

[Andrey Petrov]

Andrey Petrov ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13703

-gerrit

commit a65e6b3228ef01fb38e88681ab06e694cda48136
Author: Andrey Petrov 
Date:   Fri Feb 12 13:26:57 2016 -0800

soc/intel/apollolake: bootblock: implement platform_prog_run()

Once bootblock copied romstage into CAR it may not jump into it right
    away. This is because we are in NEM mode, there is no backing store
    and a miss in L1 may cause L1D line snoop that gets written back. The
    solution is to flush L1D to L2 so snoop guaranteed to hit L2.

Additionally, this change imports main() header for lib/bootblock.c.

Change-Id: I2ffe46dbfdfe7f0ccd38b34ff203ff76b6d5755b
    Signed-off-by: Andrey Petrov 
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 31 +++++++++++++++++++++++++-
 src/soc/intel/apollolake/include/soc/cpu.h     |  1 +
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index d3a78e1..814c8f3 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -12,15 +12,34 @@
 #include <arch/cpu.h>
 #include <bootblock_common.h>
 #include <device/pci.h>
+#include <program_loading.h>
+#include <soc/iomap.h>
 #include <soc/bootblock.h>
+#include <soc/cpu.h>
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>

+static void disable_watchdog(void)
+{
+	uint32_t reg;
+	device_t dev = PMC_DEV;
+
+	/* Open up an IO window */
+	pci_write_config32(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
+	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+	/* We don't have documentation for this bit, but it prevents reboots */
+	reg = inl(ACPI_PMIO_BASE + 0x68);
+	reg |= 1 << 11;
+	outl(reg, ACPI_PMIO_BASE + 0x68);
+}
+
+
 void asmlinkage bootblock_c_entry(void)
 {
    device_t dev = NB_DEV_ROOT;

-	/* Set PCI Express BAR */
+	/* Set PCI Express BAR and enable */
    pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);

dev = P2SB_DEV;
@@ -29,6 +48,16 @@ void asmlinkage bootblock_c_entry(void)
    pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
    pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);

+	disable_watchdog();
+
    /* Call lib/bootblock.c main */
    main();
 }
+
+void platform_prog_run(struct prog *prog)
+{
+	/* Flush L1D cache to L2 */
+	msr_t msr = rdmsr(MSR_POWER_MISC);
+	msr.lo |= (1 << 8);
+	wrmsr(MSR_POWER_MISC, msr);
+}
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index bee58b2..870f474 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -18,6 +18,7 @@
 #define CPUID_APOLLOLAKE_A0	0x506c8

#define MSR_PLATFORM_INFO	0xce
+#define MSR_POWER_MISC		0x120

#define BASE_CLOCK_MHZ		100