[coreboot-gerrit] Change in coreboot[master]: mb/intel/kblrvp/var/rvp8: Relocate devicetree FSP settings

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43911 )

Change subject: mb/intel/kblrvp/var/rvp8: Relocate devicetree FSP settings
......................................................................

mb/intel/kblrvp/var/rvp8: Relocate devicetree FSP settings

Some settings are suspicious and have been marked with FIXME comments.

Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.

Change-Id: Iea8d4a61c639081647cd539404d2809159e42bc5
Signed-off-by: Angel Pons 
---
M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
1 file changed, 49 insertions(+), 44 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43911/1

diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index f15072c..0ed0237 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -5,9 +5,6 @@
    register "deep_s3_enable_dc" = "0"

# FSP Configuration
-	register "ScsEmmcEnabled" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "PmTimerDisabled" = "0"

register "serirq_mode" = "SERIRQ_CONTINUOUS"
@@ -80,24 +77,6 @@
    	.voltage_limit = 0 \
    }"

-	# Enable Root port.
-	register "PcieRpEnable[3]" = "1"
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[8]" = "1"
-	register "PcieRpEnable[16]" = "1"
-
-	# Enable CLKREQ#
-	register "PcieRpClkReqSupport[3]" = "1"
-	register "PcieRpClkReqSupport[4]" = "1"
-	register "PcieRpClkReqSupport[8]" = "1"
-	register "PcieRpClkReqSupport[16]" = "1"
-
-	# SRCCLKREQ#
-	register "PcieRpClkReqNumber[3]" = "2"
-	register "PcieRpClkReqNumber[4]" = "1"
-	register "PcieRpClkReqNumber[8]" = "6"
-	register "PcieRpClkReqNumber[16]" = "7"
-
    register "usb2_ports[0]" = "USB2_PORT_MAX(OC2)"	    # Type-C Port
    register "usb2_ports[1]" = "USB2_PORT_MAX(OC5)"	    # Front panel
    register "usb2_ports[2]" = "USB2_PORT_MAX(OC4)"	    # Back panel
@@ -126,19 +105,6 @@

register "SsicPortEnable" = "1" # Enable SSIC for WWAN

-	register "EnableSata" = "1"
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable" = "{ \
-		[0]	= 1, \
-		[1]	= 1, \
-		[2]	= 1, \
-		[3]	= 1, \
-		[4]	= 1, \
-		[5]	= 1, \
-		[6]	= 1, \
-		[7]	= 1, \
-	}"
-
    # Must leave UART0 enabled or SD/eMMC will not work as PCI
    register "SerialIoDevMode" = "{ \
    	[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
@@ -159,25 +125,64 @@
    	.tdp_pl2_override = 25,
    }"

-	# Use default SD card detect GPIO configuration
-	#register "sdcard_cd_gpio_default" = "GPP_D10"
-
    device domain 0 on
-		device pci 17.0 on  end # SATA
+		device pci 17.0 on      # SATA
+			register "EnableSata" = "1"
+			register "SataSalpSupport" = "1"
+			register "SataPortsEnable" = "{ \
+				[0]	= 1, \
+				[1]	= 1, \
+				[2]	= 1, \
+				[3]	= 1, \
+				[4]	= 1, \
+				[5]	= 1, \
+				[6]	= 1, \
+				[7]	= 1, \
+			}"
+		end
    	device pci 19.1 on  end # I2C #5
    	device pci 1c.0 off end # PCI Express Port 1
    	device pci 1c.2 on  end # PCI Express Port 3
-		device pci 1c.3 on  end # PCI Express Port 4
-		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.3 on      # PCI Express Port 4
+			register "PcieRpEnable[3]" = "1"
+			register "PcieRpClkReqSupport[3]" = "1"
+			register "PcieRpClkReqNumber[3]" = "2"
+		end
+		device pci 1c.4 on      # PCI Express Port 5
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqNumber[4]" = "1"
+		end
+
+		# The device entry for this is in the devicetree.
+		register "PcieRpEnable[8]" = "1"
+		register "PcieRpClkReqSupport[8]" = "1"
+		register "PcieRpClkReqNumber[8]" = "6"
+
+		# FIXME: Corresponding device missing
+		register "PcieRpEnable[16]" = "1"
+		register "PcieRpClkReqSupport[16]" = "1"
+		register "PcieRpClkReqNumber[16]" = "7"
+
    	device pci 1e.1 on  end # UART #1
    	device pci 1e.2 on  end # GSPI #0
    	device pci 1e.3 on  end # GSPI #1
-		device pci 1e.4 off end # eMMC
-		device pci 1f.0 on
+		device pci 1e.4 off     # eMMC
+			register "ScsEmmcEnabled" = "0"
+			register "ScsEmmcHs400Enabled" = "0"
+		end
+
+		# FIXME: Corresponding device is not disabled
+		register "ScsSdCardEnabled" = "0"
+
+		device pci 1f.0 on      # LPC Interface
    		#chip drivers/pc80/tpm
    		#	device pnp 0c31.0 on end
    		#end
-		end # LPC Interface
-		device pci 1f.6 on  end # GbE
+		end
+		device pci 1f.6 on      # GbE
+
+			# FIXME: EnableLan is not set
+		end
    end
 end