Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47230 )
Change subject: mb/google/dedede/var/drawcia: Remove camera EEPROM power resource ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47230/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47230/2//COMMIT_MSG@11 PS2, Line 11: while accessing the camera EEPROM.
Does this mean that the camera module design keeps the EEPROM and related I2C lines always on?
Based on the comment here: https://issuetracker.google.com/issues/167938257#comment128 and the data sheet for TFC and LVI modules, as long as the 1.8V rail is up and WCAM_RST_L routed to XSHUTDN is asserted/low, then EEPROM is accessible.
The 1.2 V and 2.8 V rails used to enable the camera sensors and VCM are not required.
FW & SW does not have the ability to control the 1.8V rail. WCAM_RST_L is inited to '0' as part of GPIO configuration in coreboot.