Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47024 )
Change subject: soc/intel/broadwell: Clean up cosmetics ......................................................................
soc/intel/broadwell: Clean up cosmetics
To ease merging with Lynxpoint, define the port mask. Also simplify several register operations and drop outdated `Set timings` comment.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I6fd5516b33fe4c3d7099651ec452359030b8d509 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 16 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/47024/1
diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index f63d4ba..3ed136b 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -13,6 +13,8 @@ #include "rcba.h" #include "sata.h"
+#define SATA_PORT_MASK 0x0f + static inline u32 sir_read(struct device *dev, int idx) { pci_write_config32(dev, SATA_SIRI, idx); @@ -43,13 +45,12 @@ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a);
- /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0xf; + reg16 &= ~SATA_PORT_MASK; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); udelay(2); @@ -61,13 +62,12 @@ reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ pci_write_config32(dev, 0x98, reg32);
- /* Setup register 9Ch */ - reg16 = (1 << 5); /* BWG step 12 */ - pci_write_config16(dev, 0x9c, reg16); + /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ + pci_write_config16(dev, 0x9c, 1 << 5);
/* SATA Initialization register */ reg32 = 0x183; - reg32 |= (config->sata_port_map ^ 0xf) << 24; + reg32 |= (config->sata_port_map ^ SATA_PORT_MASK) << 24; reg32 |= (config->sata_devslp_mux & 1) << 15; pci_write_config32(dev, 0x94, reg32);
@@ -95,7 +95,7 @@ } else { /* Enable DEVSLP */ reg32 = read32(abar + 0x24); - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + reg32 |= (1 << 5) | (1 << 4)|(1 << 3)|(1 << 2); write32(abar + 0x24, reg32);
for (port = 0; port < 4; port++) { @@ -112,10 +112,10 @@ */ reg32 = RCBA32(0x3a84); /* Port 3 and 2 disabled */ - if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) + if ((config->sata_port_map & ((1 << 3) | (1 << 2))) == 0) reg32 |= (1 << 24) | (1 << 26); /* Port 1 and 0 disabled */ - if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) + if ((config->sata_port_map & ((1 << 1) | (1 << 0))) == 0) reg32 |= (1 << 20) | (1 << 18); RCBA32(0x3a84) = reg32;
@@ -239,29 +239,22 @@ reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32);
- reg32 = pci_read_config32(dev, 0x98); - reg32 |= 1 << 29; - pci_write_config32(dev, 0x98, reg32); + pci_or_config32(dev, 0x98, 1 << 29);
/* Register Lock */ - reg32 = pci_read_config32(dev, 0x9c); - reg32 |= (1 << 31); - pci_write_config32(dev, 0x9c, reg32); + pci_or_config32(dev, 0x9c, 1 << 31); }
-/* - * Set SATA controller mode early so the resource allocator can - * properly assign IO/Memory resources for the controller. - */ static void sata_enable(struct device *dev) { /* Get the chip configuration */ const struct soc_intel_broadwell_pch_config *config = config_of(dev); - u16 map = 0x0060;
- map |= (config->sata_port_map ^ 0xf) << 8; - - pci_write_config16(dev, 0x90, map); + /* + * Set SATA controller mode early so the resource allocator can + * properly assign IO/Memory resources for the controller. + */ + pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ SATA_PORT_MASK) << 8); }
static struct device_operations sata_ops = {