Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4216
-gerrit
commit 7e9a6e7fa627f369442d55afcd23a9705cb5b884 Author: Aaron Durbin adurbin@chromium.org Date: Thu May 30 10:40:54 2013 -0500
haswell: check for clean reset
When an INIT# is delivered to the CPU the CPU starts executing from the reset vector. However, the internal state is maintained. Therefore, check for such a condition and reset the system.
Issues 'apreset warm' on the EC console. INIT# is sent and CPU notices it's not a clean reset and forces one. No hangs.
Change-Id: I71229e0e5015ba8c60f5989c533268604ecc1ecc Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/57111 Reviewed-by: Duncan Laurie dlaurie@chromium.org --- src/cpu/intel/haswell/bootblock.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index bb065c8..e502cfa 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -112,10 +112,28 @@ static void set_flex_ratio_to_tdp_nominal(void) } }
+static void check_for_clean_reset(void) +{ + msr_t msr; + msr = rdmsr(MTRRdefType_MSR); + + /* Use the MTRR default type MSR as a proxy for detecting INIT#. + * Reset the system if any known bits are set in that MSR. That is + * an indication of the CPU not being properly reset. */ + if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) { + outb(0x0, 0xcf9); + outb(0x6, 0xcf9); + while (1) { + asm("hlt"); + } + } +} + static void bootblock_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); + check_for_clean_reset(); enable_rom_caching(); intel_update_microcode_from_cbfs(); }