[coreboot-gerrit] Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration

[Subrata Banik (Code Review)]

Attention is currently required from: Marc Jones, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63630 )

Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
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Patch Set 3:

(1 comment)

File src/soc/intel/common/pch/lockdown/lockdown.c:

https://review.coreboot.org/c/coreboot/+/63630/comment/dbb8c636_ab40880b 
PS3, Line 103: lpc_set_eiss
> This should do the same as fast_spi_lockdown_cfg(). I think that lpc_enable_wp() needs to be added to match.

make sense to me as I could see the same register snapshot there for eSPI/LPC as well.