[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add dq_pins_interleaved to 'struct mb_cfg'

[Subrata Banik (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46873

to look at the new patch set (#4).

Change subject: soc/intel/alderlake: Add dq_pins_interleaved to 'struct mb_cfg'
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soc/intel/alderlake: Add dq_pins_interleaved to 'struct mb_cfg'

List of changes:
1. Split mem_cfg for DDR4 and LPDDR4 as per board_id
2. Move dq_pins_interleaved into board-specific memory configuration
information

TEST=Able to build and boot DDR4 and LPDDR4 ADLRVP SKUs.

Change-Id: I6ef19209767c810426bba0c8bc48178bf2e2a110
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
M src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c
M src/soc/intel/alderlake/include/soc/meminit.h
M src/soc/intel/alderlake/meminit.c
4 files changed, 31 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46873/4