[coreboot-gerrit] Change in coreboot[master]: mainboard/volteer: enable early tcss chrome ec related code in mainboard

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45742 )

Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard
......................................................................

mainboard/volteer: enable early tcss chrome ec related code in mainboard

Since mainboard is the determining factor if a board uses chrome ec or not
moving the early tcss code that relies on chrome ec from soc code to mainboard.

BUG=b:151731851
BRANCH=none
TEST=Built and verified that external display is coming up during recovery

Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12
Signed-off-by: Brandon Breitenstein 
---
M src/mainboard/google/volteer/mainboard.c
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
2 files changed, 76 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/1

diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index 23c3e92..80a04d0 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -5,9 +5,11 @@
 #include <baseboard/variants.h>
 #include <device/device.h>
 #include <drivers/spi/tpm/tpm.h>
+#include <ec/google/chromeec/ec.h>
 #include <ec/ec.h>
 #include <fw_config.h>
 #include <security/tpm/tss.h>
+#include <soc/early_tcss.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -65,6 +67,78 @@
    }
 }

+void mainboard_early_tcss_enable(void)
+{
+	uint8_t dp_mode;
+	unsigned int num_ports;
+	int ret, i;
+	bool ufp, acc;
+
+	ret = google_chromeec_get_num_pd_ports(&num_ports);
+	if (ret < 0) {
+		printk(BIOS_ERR, "get_num_pd_ports failed unable to continue\n");
+		return;
+	}
+
+	for (i = 0; i < num_ports; i++) {
+		uint8_t port_map, mux_flags;
+		struct tcss_mux mux_data;
+
+		ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags);
+		if (ret < 0) {
+			printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i);
+			continue;
+		}
+
+		ret = google_chromeec_pd_get_port_info(i, &port_map);
+		if (ret < 0) {
+			printk(BIOS_ERR, "port C%d: get_port_info failed\n", i);
+			continue;
+		}
+
+		mux_data.usb2_port = port_map & USB_2_PORT_MASK;
+		mux_data.usb3_port = (port_map & USB_3_PORT_MASK) >> 4;
+
+		//Add check for connected maybe?
+
+		ret = google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode);
+		if (ret < 0) {
+			printk(BIOS_ERR, "port C%d: pd_control failed\n", i);
+			continue;
+		}
+
+		mux_data.usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED);
+		mux_data.dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED);
+		mux_data.cable = !!(mux_flags & USB_PD_CTRL_ACTIVE_CABLE);
+		mux_data.polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED);
+		mux_data.hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ);
+		mux_data.hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL);
+		mux_data.ufp = !!ufp;
+		mux_data.acc = !!acc;
+		mux_data.dp_mode = dp_mode;
+
+		printk(BIOS_DEBUG, "Port %d mux=0x%x\n"
+				"USB2 port = %x\n"
+				"USB3 port = %x\n"
+				"DP Mode = %x\n"
+				"dp = %d\n"
+				"usb = %d\n"
+				"cable = %d\n"
+				"polarity = %d\n"
+				"hpd_lvl = %d\n"
+				"hpd_irq = %d\n"
+				"ufp = %d\n"
+				"dbg_acc = %d\n",
+				i, (unsigned int)mux_flags, mux_data.usb2_port,
+				mux_data.usb3_port, mux_data.dp_mode, mux_data.dp,
+				mux_data.usb, mux_data.cable, mux_data.polarity,
+				mux_data.hpd_lvl, mux_data.hpd_irq, mux_data.ufp,
+				mux_data.acc);
+
+		update_tcss_mux(i, mux_data);
+	}
+}
+
 static void mainboard_chip_init(void *chip_info)
 {
    const struct pad_config *base_pads;
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 43ba255..179aeb0 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -59,6 +59,8 @@
    register "SaGv" = "SaGv_Enabled"
    register "SmbusEnable" = "0"

+	register "RMT" = "1"
+
    register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
    register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A1
    register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN