Attention is currently required from: Jérémy Compostella, Pranava Y N.
Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84408?usp=email )
Change subject: mb/google/fatcat: Add FW_CONFIG ......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84408/comment/9179c015_103394fe?usp... : PS1, Line 2: field DEBUG 0 1 : option NONE 0 : option RMT 1 : end why we need to use FW_CONFIG for debug feature ?
https://review.coreboot.org/c/coreboot/+/84408/comment/558d1428_bc3fd9fa?usp... : PS1, Line 1: fw_config : field DEBUG 0 1 : option NONE 0 : option RMT 1 : end : field AUDIO 8 10 : option NONE 0 : option PTL_ALC1019_ALC5682I_I2S 1 : option PTL_MAX98373_ALC5682_SNDW 2 : option PTL_ALC722_SNDW 3 : option PTL_ALC5682I_MAX9857A_I2S 4 : option PTL_ALC256_HDA 5 : option PTL_MAX98360_ALC5682I_I2S 6 : end : field WIFI 11 : option WIFI_CNVI 0 : option WIFI_PCIE 1 : end : field TOUCHSCREEN 12 14 : option NONE 0 : option I2C4 1 : option GSPI0 2 : option THC0_SPI 3 : option THC0_I2C 4 : end : field TOUCHPAD 16 18 : option NONE 0 : option THC1I2C_HYNITRON 1 : option I2C5_HYNITRON 2 : end : field X1SLOT 19 20 : option NONE 0 : option SD 1 : option ETH 2 : end : field STORAGE 21 22 : option TOP_NVME 0 # RP5 : option BOTTOM_NVME 1 # RP9 : option UFS 2 : end : field FPS 23 24 : option NONE 0 : option SPI 1 : option USB2 2 : end : field WWAN 25 26 : option NONE 0 : option PCIE 1 : option USB 2 : end : field CNVI_BT 27 : option BT_USB 0 : option BT_PCIE 1 : end : end : what is the source of truth here ? please hold on FW config CL as we need to work with YH/HW folks to conclude that SKU configuration first then we will decide the FW_CONFIG depending on BoM configuration.
I don't think we need to use X1SLOT, TOUCHPAD, TOUCHSCREEN, CNVI_BT (is always USB for cros), FPS (always SPI), DEBUG etc.