Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50893 )
Change subject: soc/amd/cezanne/acpi: Add pci0.asl ......................................................................
soc/amd/cezanne/acpi: Add pci0.asl
This differs slightly from picasso. The PCI BAR region is between TOM1 and CONFIG_MMCONF_BASE_ADDRESS. This patches what the Intel platforms are doing. It also matches what linux derives from the e820 tables:
[mem 0xd0000000-0xf7ffffff] available for PCI devices
Picasso currently declares the region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region.
TEST=Boot majolica and check logs pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff] pci_bus 0000:00: root bus resource [bus 00-3f]
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I4ff02012795e2166e3a4197071b1136727089318 --- A src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/cezanne/acpi/soc.asl M src/soc/amd/cezanne/root_complex.c 3 files changed, 90 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/50893/1
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl new file mode 100644 index 0000000..8ffc063 --- /dev/null +++ b/src/soc/amd/cezanne/acpi/pci0.asl @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(PCI0) { + Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ + Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ + External(TOM1, IntObj) /* Generated by root_complex.c */ + + Method(_BBN, 0, NotSerialized) { + Return(Zero) /* Bus number = 0 */ + } + + Method(_STA, 0, NotSerialized) { + Return(0x0B) /* Status is visible */ + } + + /* Operating System Capabilities Method */ + Method(_OSC, 4) { + CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ + + /* Check for proper PCI/PCIe UUID */ + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { + /* Let OS control everything */ + Return (Arg3) + } Else { + CDW1 |= 4 /* Unrecognized UUID */ + Return (Arg3) + } + } + Name(CRES, ResourceTemplate() { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00ff, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + + IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0cf7, /* range maximum */ + 0x0000, /* translation */ + 0x0cf8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0d00, /* range minimum */ + 0xffff, /* range maximum */ + 0x0000, /* translation */ + 0xf300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) + + Method(_CRS, 0) { + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ + MM1B = TOM1 + Local0 = CONFIG_MMCONF_BASE_ADDRESS + Local0 -= TOM1 + MM1L = Local0 + + CreateWordField(CRES, ^PSB0._MAX, BMAX) + CreateWordField(CRES, ^PSB0._LEN, BLEN) + BMAX = CONFIG_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_MMCONF_BUS_NUMBER + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + +} /* End PCI0 scope */ diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index 1a45b0a..c935dc3 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -9,6 +9,8 @@ #include "pci_int_defs.asl"
#include "mmio.asl" + + #include "pci0.asl" } /* End _SB scope */
#include <soc/amd/common/acpi/platform.asl> diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 9191dc2..ba84681 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/acpi.h> #include <amdblocks/memmap.h> #include <cbmem.h> #include <console/console.h> @@ -130,6 +131,11 @@ } }
+static void root_complex_fill_ssdt(const struct device *device) +{ + acpi_fill_root_complex_tom(device); +} + static const char *gnb_acpi_name(const struct device *dev) { return "GNB"; @@ -140,6 +146,7 @@ .set_resources = noop_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_name = gnb_acpi_name, + .acpi_fill_ssdt = root_complex_fill_ssdt, };
static const struct pci_driver family17_root_complex __pci_driver = {