[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell/chip.h: Drop unused fields

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46995 )

Change subject: soc/intel/broadwell/chip.h: Drop unused fields
......................................................................

soc/intel/broadwell/chip.h: Drop unused fields

Broadwell boards now use the CPU code for Haswell. Therefore, these
devicetree options are no longer used anywhere and can be removed.

Change-Id: Ib0d1b6eecc11a70d1a2614669353a8040c860535
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46995
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
Reviewed-by: Michael Niewöhner 
---
M src/soc/intel/broadwell/chip.h
1 file changed, 0 insertions(+), 28 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 9f6c58d..045fdbc 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -31,34 +31,6 @@
    int cdclk;

struct i915_gpu_controller_info gfx;
-
-	/*
-	 * Minimum voltage for C6/C7 state:
-	 * 0x67 = 1.6V (full swing)
-	 *  ...
-	 * 0x79 = 1.7V
-	 *  ...
-	 * 0x83 = 1.8V (no swing)
-	 */
-	int vr_cpu_min_vid;
-
-	/*
-	 * Set slow VR ramp rate on C-state exit:
-	 * 0 = Fast VR ramp rate / 2
-	 * 1 = Fast VR ramp rate / 4
-	 * 2 = Fast VR ramp rate / 8
-	 * 3 = Fast VR ramp rate / 16
-	 */
-	int vr_slow_ramp_rate_set;
-
-	/* Enable slow VR ramp rate */
-	int vr_slow_ramp_rate_enable;
-
-	/* Enable S0iX support */
-	int s0ix_enable;
-
-	/* TCC activation offset */
-	uint32_t tcc_offset;
 };

typedef struct soc_intel_broadwell_config config_t;