Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58283 )
Change subject: sb/intel/lynxpoint: Clarify PCIe Non Common Clock mode ......................................................................
sb/intel/lynxpoint: Clarify PCIe Non Common Clock mode
The "force ASPM" setting actually controls Non Common Clock mode with Spread Spectrum Clocking. Rename the associated variables accordingly and expand the comments according to document 535127 (BDW PCH-LP BS).
Change-Id: I54e1c3fedd47e7df18b9d4feb0ca7d8636e8236f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/pcie.c 4 files changed, 21 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/58283/1
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8c54f6a..1644115 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -40,8 +40,8 @@ register "sata_port_map" = "0x1" register "sata_devslp_disable" = "0x1"
- # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" + # Force enable Non Common Clock mode with SSC for PCIe Port 4 + register "pcie_port_force_ncc_ssc" = "0x10"
# Enable port coalescing register "pcie_port_coalesce" = "1" diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index d989545..e7c6e3a 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -47,8 +47,8 @@ register "sio_i2c0_voltage" = "0" # 3.3V register "sio_i2c1_voltage" = "0" # 3.3V
- # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" + # Force enable Non Common Clock mode with SSC for PCIe Port 1 + register "pcie_port_force_ncc_ssc" = "0x01"
# Route all USB ports to XHCI per default register "xhci_default" = "1" diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 89bbb1c..45f2fe6 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -67,8 +67,8 @@ /* Enable linear PCIe Root Port function numbers starting at zero */ uint8_t pcie_port_coalesce;
- /* Force root port ASPM configuration with port bitmap */ - uint8_t pcie_port_force_aspm; + /* Force root port Non-Common Clock mode with SSC with port bitmap */ + uint8_t pcie_port_force_ncc_ssc;
/* Put SerialIO devices into ACPI mode instead of a PCI device */ uint8_t sio_acpi_mode; diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 3d8bb79..271f7c8 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -502,7 +502,7 @@ static void pch_pcie_early(struct device *dev) { struct southbridge_intel_lynxpoint_config *config = dev->chip_info; - int do_aspm = 0; + int pcie_ncc_ssc = 0; int rp = root_port_number(dev); int is_lp = pch_is_lp();
@@ -516,21 +516,21 @@ * Bits 31:28 of b0d28f0 0x32c register correspond to * Root Ports 4:1. */ - do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); + pcie_ncc_ssc = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); break; case 5: /* * Bit 28 of b0d28f4 0x32c register corresponds to * Root Port 5. */ - do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); + pcie_ncc_ssc = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: /* * Bit 29 of b0d28f5 0x32c register corresponds to * Root Port 6. */ - do_aspm = !!(rpc.b0d28f5_32c & (1 << 29)); + pcie_ncc_ssc = !!(rpc.b0d28f5_32c & (1 << 29)); break; } } else { @@ -543,7 +543,7 @@ * Bits 31:28 of b0d28f0 0x32c register correspond to * Root Ports 4:1. */ - do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); + pcie_ncc_ssc = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); break; case 5: case 6: @@ -553,25 +553,26 @@ * Bits 31:28 of b0d28f4 0x32c register correspond to * Root Ports 8:5. */ - do_aspm = !!(rpc.b0d28f4_32c & (1 << (28 + rp - 5))); + pcie_ncc_ssc = !!(rpc.b0d28f4_32c & (1 << (28 + rp - 5))); break; } }
- /* Allow ASPM to be forced on in devicetree */ - if (config && (config->pcie_port_force_aspm & (1 << (rp - 1)))) - do_aspm = 1; + /* Allow Non Common Clock mode with Spread Spectrum to be forced on in devicetree */ + if (config && (config->pcie_port_force_ncc_ssc & (1 << (rp - 1)))) + pcie_ncc_ssc = 1;
- printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n", - rp, do_aspm ? "en" : "dis"); + printk(BIOS_DEBUG, "PCIe Root Port %d Non Common Clock mode with SSC is %sabled\n", + rp, pcie_ncc_ssc ? "en" : "dis");
- if (do_aspm) { - /* Set ASPM bits in MPC2 register. */ + if (pcie_ncc_ssc) { + /* Disable ASPM L0s support in MPC2 register. */ pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));
/* Set unique clock exit latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
+ /* Increase the elastic buffer pointer half full pointer values by 2. */ if (is_lp) { switch (rp) { case 1: @@ -649,7 +650,7 @@ pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
/* Set L1 exit latency in LCAP register. */ - if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm) + if ((pci_read_config8(dev, 0xf5) & 0x1) || pcie_ncc_ssc) pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));